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| cr1901_modern | daveshah: Would it, in principle, be possible to build an ice40/ecpbram that targets a distributed ROM or "LUTs being used as ROMs" (when a BRAM would be a waste, but you don't want to resynth your design just to change a set of LUT values)? | 22:25 |
|---|---|---|
| mwk | cr1901_modern: I have something like this on my TODO list | 22:27 |
| mwk | it's... nontrivial | 22:27 |
| mwk | and doing it properly would require cooperation of many levels of the stack | 22:28 |
| daveshah | The approach icebram etc doesn't work as 16 bits isn't enough entropy | 22:28 |
| daveshah | *icebram etc uses | 22:28 |
| cr1901_modern | I was afraid of that... doesn't _sound_ nontrivial from a 5000 ft. view. Hence why I asked. | 22:28 |
| mwk | well the idea is simple | 22:28 |
| * cr1901_modern nods | 22:28 | |
| mwk | thread something like "relocation markers" all the way from yosys to some kind of annotation file for the bitstream | 22:28 |
| mwk | but it requires changing a lot of places | 22:29 |
| cr1901_modern | Ahhh, hmmm... well, I'll live without then. | 22:29 |
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| cr1901_modern | Context is I have a big ROM whose starting location is indexed by a little ROM. I don't want the little ROM to use BRAM resources for multiple reasons: async read is desireable, and the little ROM's too little anyway. | 22:30 |
| mwk | right | 22:30 |
| cr1901_modern | But if I change the big ROM's contents, then the chance of little ROM's contents needing to change is very high too :( | 22:30 |
| mwk | what I'm saying is... I really like the idea of having something like this, and I know how to do this | 22:30 |
| cr1901_modern | Ahhh :D | 22:31 |
| mwk | but it takes *a lot* of work and needs support from pretty much every piece of software in the chain | 22:31 |
| cr1901_modern | I'll just hardcode little ROM for now and live w/ the inefficiency of missing big ROM entries | 22:31 |
| mwk | lots of it per-platform even | 22:31 |
| mwk | I'm toying with the idea of implementing the first part now (since I'm doing a big memory inference rewrite in yosys anyway), but it's going to be pretty useless until we have support in every link of the chain for at least one platform | 22:32 |
| cr1901_modern | what would it look like at the source/RTLIL level? An attribute? | 22:33 |
| mwk | yeah, I guess | 22:33 |
| mwk | an attribute of "actually this RAM's init value should be the following bits of this parameter, to be substituted in the future" | 22:35 |
| cr1901_modern | interesting | 22:36 |
| mwk | memory inference would need to propagate it correctly when splitting up the RAM to multiple blocks; optimization passes would need to look at it to avoid optimizing things based on the init value; nextpnr would basically need to record all of them in some kind of annotation file produced along with the bitstream that the packer could then use to fill in the values | 22:36 |
| cr1901_modern | Okay, that's definitely a lot of work... I can certainly live without right now. | 22:37 |
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