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| z0ttel | Can I access module parameter names from assertions of a higher-level module like this? https://gist.github.com/Zottel/72d281b9ddc8cf614f16dc74327c65c1 | 10:13 |
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| z0ttel | Wanted to make my wiring part of the verification, but I appear to be missing some detail there... | 10:16 |
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| z0ttel | Okay, on eigth glance, the "no driver" warnings show only for one signal that really is not driven and the submodule ports. Since all assertions pass once I use wires instead of submodule ports I assume it's not possible to access those in that context. | 12:26 |
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| develonepi3 | Hello All: I recenlty was able to create System Verilog files that create cpus risc-v_1-stage and risc-v_4-stage with mul/div and without mul/div. This uses sandpiper in the cloud. This requires "https://github.com/stevehoover/warp-v" Using yosys for synth_ice40 creates warp-v_risc-v_4-stage.blif, and warp-v_risc-v_4-stage.json creates warp-v_risc-v_1-stage.blif, and warp-v_risc-v_1-stage.json and simple.log for all 4 cases. Results are found | 20:46 |
| develonepi3 | "https://github.com/develone/sandpiper_test/tree/master/risc-v_cpus" SB_LUT4 7607 RISC-V 4 stage pipeline with mul/div enable. SB_LUT4 4116 RISC-V 4 stage pipeline with mul/div disable. creates warp-v_risc-v_4-stage.blif, and warp-v_risc-v_4-stage.json | 20:46 |
| develonepi3 | creates warp-v_risc-v_1-stage.blif, and warp-v_risc-v_1-stage.json SB_LUT4 1837 RISC-V 1 stage pipeline with mul/div disable. | 20:46 |
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