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| tnt | :/ Is there something more to do that adding 'multiclock on' in the .sby for riscv formal to behavre properly with @negedge in the design ? | 17:16 |
|---|---|---|
| tnt | without it I get 'FAIL' for the reg_ch0 test. With it on, I get 'PASS' ... but I get PASS also if I voluntarely add a bug in my register implementation so that doesn't inspire much confidence that the testing is working. | 17:16 |
| daveshah | You may need to double all the bmc depths too | 17:18 |
| daveshah | With multiclock on, it will be two solver steps per clock cycle | 17:18 |
| tnt | ok, I doubled `depth` and `skip` | 17:19 |
| tnt | Ok, it failed on the purposefully buggy implementation, good first step. Lets see how it does on the (hopefully) correct one. | 17:28 |
| tnt | Arf, failed :/ | 17:30 |
| tnt | And the trace vcd is showing me nothing AFAICT. I mean the register write enable is low for the entire trace so not sure what's it expecting there. | 17:56 |
| daveshah | It might be to do with skip and the fact that multiclock gives it the freedom to keep the clock stuck not toggling | 17:58 |
| daveshah | You might need to constrain the clock, although this is slightly beyond my formal experience | 17:58 |
| tnt | In the vcd at least I see it toggling regularely. | 17:59 |
| daveshah | Ah, that probably isn't the problem then | 17:59 |
| tnt | Shure SM7b | 17:59 |
| tnt | https://i.imgur.com/h3cYuZX.png | 18:00 |
| tnt | (sorry bad cut & paste ... ) | 18:00 |
| Lofty | tnt: always preferred the SM57 myself /s | 18:16 |
| tnt | :) | 18:20 |
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| tnt | ¯\_(ツ)_/¯ I guess the fact it seems to run software just fine will have to be good enough. | 18:53 |
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