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| tnt | I'm not sure how 'specify' works in the ice40 cells_sim, but in SB_RAM40_4KNR for instance that has reads on the falling edge of the clock, should all the `specify` lines use negedge instead of posedge ? | 13:02 |
|---|---|---|
| daveshah | Really it's only purpose is for abc9, and I don't know if that even understands clock edges | 13:04 |
| daveshah | For timing simulations it might well need to be negedge, but they haven't really been tested much anyway | 13:04 |
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| tnt | also looking at the numbers it's interesting to see the up5k is actually faste ck-to-out for EBR than the HX ? | 13:07 |
| daveshah | Yeah | 13:10 |
| daveshah | Maybe it's a newer version of the memory compiler or something | 13:10 |
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| tnt | Anyone familiar with riscv-formal ? I've run the picorv32 tests from the quickstart guide, 2 of them failed but it's a known issue but then reg_ch0 is just taking forever. It's at ~ 40 min now while the other 60 tests finished (all together) in ~ 10 min total. | 20:41 |
| Lofty | tnt: maybe ask Tom Verbeure on Twitter | 20:50 |
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