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| kitten_nb_five | Hell World! I am just beginning to learn Verilog and FPGA-stuff and i really appreciate the FOSS-toolchain. Thank you! | 16:48 |
|---|---|---|
| kitten_nb_five | I have a problem but i am not sure if this is wrong syntax or sth with yosys. Maybe somebody can tell me? [...] | 16:49 |
| kitten_nb_five | I have a definition of a module and i want to create an instance of this module with a parameter | 16:50 |
| kitten_nb_five | This works/"compiles": mod_div #(.pDivider(25_000_000)) div_slow(.clk(clk_25M), .clk_div(out_slow)); | 16:50 |
| kitten_nb_five | This gives me an error, so is this valid Verilog or not? mod_div #(parameter pDivider=25_000_000) div_slow(.clk(clk_25M), .clk_div(out_slow)); | 16:50 |
| tnt | no | 16:50 |
| kitten_nb_five | ok, ty! | 16:51 |
| kitten_nb_five | Another question if you allow: Is there a way to make yosys return a non-zero exitcode in case of any warnings, like -Werror for the GCC? This would be useful for chaining commands (Linux): yosys ... && nextpnr ... | 16:55 |
| tnt | no idea | 16:55 |
| tnt | but given some yosys warning are both harmless and hard to get rid of, I'm not sure how useful it'd be in practice. | 16:56 |
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| kitten_nb_five | i am really just beginning to use yosys and only had "good"=meaningfull warnings. When writing software i always try to make it compile with -Werror, so i thought this might be a good idea for doing FPGA-stuff to (especially for a total beginner) | 17:00 |
| tnt | Yeah, I have the same policy for sw, but AFAIK yosys doesn't have anything like - | 17:01 |
| tnt | -Wno-xxx to disable some warnings ... | 17:01 |
| tnt | Oh my bad, it does. | 17:06 |
| tnt | -e | 17:07 |
| tnt | Allows to specify a regulat expression to turn warning into errors. (so you can make a regexp that matches everything ...) | 17:07 |
| tnt | it'll stop at the first error though AFAICT. | 17:08 |
| kitten_nb_five | ty, i did not see this one in the manual. i will give it a try | 17:08 |
| tnt | I read the source code ... not the manual :p | 17:09 |
| kitten_nb_five | -e works great! | 17:15 |
| kitten_nb_five | yosys -p "synth_ecp5 -json out.json" -q blink.v | 17:15 |
| kitten_nb_five | Warning: Wire top.\div_slow.clk is used but has no driver. | 17:15 |
| kitten_nb_five | yosys -p "synth_ecp5 -json out.json" -q -e ".*" blink.v | 17:15 |
| kitten_nb_five | ERROR: Wire top.\div_slow.clk is used but has no driver. | 17:15 |
| kitten_nb_five | ty! | 17:15 |
| kitten_nb_five | uh, that should better be ".+" | 17:16 |
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| ZipCPU | kitten_nb_five: Consider using verilator -Wall | 18:47 |
| kitten_nb_five | i don't know this one, i will look at it. ty. | 18:48 |
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