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| jeanthom | Are there any docs for DQSBUFI (ECP5)? | 20:09 |
|---|---|---|
| daveshah | You mean DQSBUFM? | 20:09 |
| jeanthom | nope | 20:10 |
| daveshah | The "high speed IO interface" pdf has some info on it | 20:10 |
| daveshah | otherwise you can read the sim model | 20:10 |
| daveshah | DQSBUFI sounds like a primitive for another device | 20:10 |
| jeanthom | http://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/1D2/FPGA-IPUG-02098-1-1-DDR3-SDRAM-PHY-Radiant-SW.ashx?document_id=52811 | 20:10 |
| jeanthom | oops not this one | 20:11 |
| jeanthom | http://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/E---I-Folder-3/FPGA-IPUG-02047-2-1-DDR3-SDRAM-Controller-IP.ashx?document_id=36115 | 20:12 |
| jeanthom | that one | 20:12 |
| jeanthom | "The ECP5 DQSBUFI block supports a dynamic READ signal positioning function called read training" | 20:12 |
| daveshah | The ECP5 native primitive is DQSBUFM | 20:12 |
| daveshah | either that is from a very early Diamond version or a typo | 20:12 |
| jeanthom | Why would it be from a very early version of Diamond? | 20:14 |
| daveshah | Perhaps, an early version had a different name, idk | 20:14 |
| daveshah | There is no DQSBUFI primitive in the Diamond 3.11 Verilog libraries anyway | 20:15 |
| jeanthom | ah, ok | 20:15 |
| jeanthom | yep I couldn't find DQSBUFI in here | 20:15 |
| jeanthom | I was wondering if it was a primitive reserved for internal use or just a typo | 20:16 |
| daveshah | Ah, it was an ECP4 primitive, I've found it in my copy of Diamond 2.0 | 20:16 |
| cr1901_modern | What, does that run on DOS or something :P? | 20:18 |
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| daveshah | https://www.latticesemi.com/en/About/Newsroom/PressReleases/2012/201207LatticeDiamond20SoftwareUnleashesPowerfulDesignTools | 20:18 |
| tpb | Title: 2012-07 - Lattice Diamond 2.0 Software Unleashes Powerful Design Tools - Lattice Semiconductor (at www.latticesemi.com) | 20:18 |
| daveshah | > twelve 6Gbps SERDES | 20:18 |
| jeanthom | Wasn't aware that the ECP4 even existed! | 20:18 |
| daveshah | it only exists in landfill | 20:18 |
| jeanthom | haha why | 20:19 |
| daveshah | perhaps a few dusty drawers of abandoned giveaway dev boards | 20:19 |
| daveshah | it was scrapped shortly after the first samples were given to customers | 20:19 |
| jeanthom | ah that's sad | 20:19 |
| daveshah | Lattice suddenly realised they couldn't compete with Xilinx et al. and decided to pivot towards cheap/really low end instead | 20:20 |
| daveshah | I have a suspicion they did some big yield optimisations between ECP4 and ECP5 | 20:21 |
| cr1901_modern | Well that wasn't that long ago... but 3.11 is a lot more than 2.0 | 20:21 |
| daveshah | If anyone does have an ECP4 dev board lying around (any big Lattice customers here??) I would love to buy it... | 20:22 |
| daveshah | At least Nexus does reintroduce a lot of the nice features from the ECP4 that the ECP5 dropped; like 8x/10x IO gearing, fabric-accessible dynamic PLL configuration, separate IO CDR blocks | 20:24 |
| awygle | if only it came cheaper | 20:33 |
| daveshah | It's hard to tell if Nexus is just super pricy or Lattice have gone for Xilinx style ludicrous single/low qty pricing - either way a shame after the ECP5 | 20:34 |
| daveshah | It would also be nice to be able to buy it at all, availability now seems to be Feb-March 2021 | 20:35 |
| jeanthom | mouser has some devboards in stock, but no chips :( | 20:36 |
| cr1901_modern | economies of scale sucks | 20:36 |
| daveshah | The current devboard stocks are also probably still ES silicon, and I believe that will be dropped in new Radiant versions - as well has having some totally undocumented set of bugs | 20:37 |
| cr1901_modern | Early Samples? | 20:38 |
| daveshah | engineering sample | 20:38 |
| awygle | i'm kind of hoping they have bad yield on all the hard IP blocks | 20:44 |
| awygle | and if we get a more vanilla fabric version it'll be cheaper | 20:44 |
| awygle | or else market-positioned lower even if not actually cheaper for them | 20:44 |
| awygle | that may be wishful thinking though | 20:44 |
| daveshah | I was hoping that with the Certus NX (removing the Mixel MIPI core) but sadly that didn't work out | 20:45 |
| daveshah | I reckon the Certus is the most vanilla-fabric one there will be | 20:45 |
| daveshah | There are two more parts planned in the near/medium future. My best guess, based on what has been hinted so far in various ways, is one iCE40 successor (small packages, low power, no SERDES/PCIe/MIPI) and one ECP5 successor (up to ~150k LUT4, SERDES and PCIe) | 20:47 |
| cr1901_modern | Where does MachXO5 fit into it? | 20:48 |
| daveshah | They'll have to get reliable flash working on their 28nm FDSOI first | 20:48 |
| daveshah | I doubt MachXO is moving soon, MachXO3D was only just released | 20:49 |
| cr1901_modern | that was also another thinly-veiled "Lattice can't count" joke :) | 20:49 |
| daveshah | Eh, PSION didn't like 4 either | 20:49 |
| cr1901_modern | 4 is a superstituous number in some parts of the world | 20:51 |
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