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| Sarayan | Is someone smarter than me capable of running a software simulation of https://github.com/ijor/fx68k ? | 08:48 |
|---|---|---|
| tpb | Title: GitHub - ijor/fx68k: FX68K 68000 cycle accurate SystemVerilog core (at github.com) | 08:48 |
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| Lofty | Sarayan: it might simulate under GHDL or something | 09:53 |
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| Sarayan | ghdl does vhdl, not system verilog | 12:35 |
| Lofty | I got it mixed up with the other m68k core which is VHDL | 12:41 |
| Sarayan | there's an other cycle-precise 68k core? | 12:43 |
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| Lofty | Sarayan: TG68K. https://opencores.org/projects/tg68 | 12:49 |
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| Lofty | https://github.com/MiSTer-devel/Minimig-AGA_MiSTer/tree/MiSTer/rtl/tg68k might be more updated, I dunno | 12:52 |
| tpb | Title: Minimig-AGA_MiSTer/rtl/tg68k at MiSTer · MiSTer-devel/Minimig-AGA_MiSTer · GitHub (at github.com) | 12:52 |
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| thardin | is it possible to have input arrays somehow besides flattening? | 13:44 |
| thardin | like input [11:0] values [0:3] | 13:44 |
| thardin | I tried using systemverilog | 13:45 |
| thardin | and using wire instead of input | 13:45 |
| Lofty | thardin: what's your use case for that? | 13:46 |
| thardin | right now I'm trying to dump some 12-bit values to an LCD as hex | 13:47 |
| Sarayan | Lofty: Not cycle-exact, just an inspired reimplementation | 13:49 |
| Lofty | https://github.com/YosysHQ/yosys/issues/2354 <-- mmm. | 15:16 |
| tpb | Title: Is there a way to specify internal pullups for the ICE40 family? · Issue #2354 · YosysHQ/yosys · GitHub (at github.com) | 15:16 |
| daveshah | https://github.com/YosysHQ/nextpnr/blob/master/docs/ice40.md | 15:24 |
| tpb | Title: nextpnr/ice40.md at master · YosysHQ/nextpnr · GitHub (at github.com) | 15:24 |
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| Sarayan | '/lastlog cuavas | 16:54 |
| Sarayan | gah | 16:54 |
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