| *** tpb has joined #yosys | 00:00 | |
| *** Degi has quit IRC | 00:21 | |
| *** Degi has joined #yosys | 00:22 | |
| *** tlwoerner has joined #yosys | 00:50 | |
| *** _whitelogger has quit IRC | 00:54 | |
| *** _whitelogger has joined #yosys | 00:56 | |
| *** emeb_mac has quit IRC | 01:02 | |
| *** emeb_mac has joined #yosys | 01:03 | |
| *** az0re has quit IRC | 01:11 | |
| *** cr1901_modern has quit IRC | 01:30 | |
| *** cr1901_modern has joined #yosys | 01:30 | |
| *** cr1901_modern has quit IRC | 01:34 | |
| *** cr1901_modern has joined #yosys | 01:35 | |
| *** az0re has joined #yosys | 01:53 | |
| *** cr1901_modern has quit IRC | 01:56 | |
| *** Cerpin has quit IRC | 02:53 | |
| *** pacak has quit IRC | 02:53 | |
| *** anuejn has quit IRC | 02:53 | |
| *** pie_ has quit IRC | 02:53 | |
| *** agg has quit IRC | 02:53 | |
| *** simeonm has quit IRC | 02:53 | |
| *** srk has quit IRC | 02:53 | |
| *** simeonm has joined #yosys | 02:54 | |
| *** srk has joined #yosys | 02:54 | |
| *** Cerpin has joined #yosys | 02:59 | |
| *** pacak has joined #yosys | 02:59 | |
| *** anuejn has joined #yosys | 02:59 | |
| *** pie_ has joined #yosys | 02:59 | |
| *** agg has joined #yosys | 02:59 | |
| *** cr1901_modern has joined #yosys | 04:12 | |
| *** az0re has quit IRC | 04:15 | |
| *** _whitelogger has quit IRC | 04:51 | |
| *** _whitelogger has joined #yosys | 04:53 | |
| *** _whitelogger has quit IRC | 05:15 | |
| *** _whitelogger has joined #yosys | 05:17 | |
| *** az0re has joined #yosys | 05:23 | |
| *** MoeIcenowy has quit IRC | 05:49 | |
| *** MoeIcenowy has joined #yosys | 05:49 | |
| *** kuldeep has quit IRC | 05:49 | |
| *** kuldeep has joined #yosys | 05:50 | |
| *** dkozel has quit IRC | 05:50 | |
| *** dkozel has joined #yosys | 05:51 | |
| *** indy has joined #yosys | 06:38 | |
| *** citypw has joined #yosys | 06:45 | |
| *** Asu has joined #yosys | 06:56 | |
| *** emeb_mac has quit IRC | 07:21 | |
| *** kraiskil has joined #yosys | 08:42 | |
| *** solidtux has quit IRC | 09:44 | |
| *** solidtux has joined #yosys | 09:47 | |
| *** kraiskil has quit IRC | 10:52 | |
| *** X-Scale` has joined #yosys | 11:46 | |
| *** X-Scale has quit IRC | 11:46 | |
| *** X-Scale` is now known as X-Scale | 11:47 | |
| pepijndevos | If I accumulate a bunch of things with a generate loop, will something in the chain balance the adder tree, or will it become a huge speed bottleneck? | 12:41 |
|---|---|---|
| mwk | alumacc will make a $macc cell out of it with shitloads of inputs | 12:43 |
| mwk | maccmap will turn it into lots of 3-to-2 adder compression stages, plus an $alu for the final stage | 12:43 |
| pepijndevos | 3-to-2 adder compression stages? | 12:44 |
| mwk | hmm, never heard of 3:2 compressor? | 12:46 |
| mwk | *sigh* I cannot seem to find a good reference for it | 12:46 |
| pepijndevos | ... maybe... it rings a very remote bell | 12:46 |
| mwk | the idea is that you have 3 numbers to add | 12:46 |
| mwk | so you use a bunch of full adders, but without a carry chain, to turn that into two numbers you have to add | 12:47 |
| *** indy has quit IRC | 12:48 | |
| pepijndevos | I remember we once had a random lecture that covered an algorithm for building the most efficient tree of what you call compressors. | 12:49 |
| mwk | the main idea here is that you still have the same amount of full adders, but only the final stage actually needs a carry chain | 12:49 |
| pepijndevos | Something weird where you assigned levels to things and had to combine things from the same levels or something | 12:50 |
| mwk | mhm | 12:50 |
| mwk | sounds like maccmap | 12:50 |
| pepijndevos | I see | 12:50 |
| pepijndevos | Long story short: it will turn into something reasonable | 12:50 |
| pepijndevos | thanks :)) | 12:50 |
| mwk | ... more or less | 12:50 |
| mwk | there's a bunch of ways that maccmap could be improved | 12:51 |
| mwk | but eh | 12:51 |
| mwk | the same could be said about every single part of yosys | 12:51 |
| pepijndevos | hrm | 12:51 |
| mwk | eg. for a LUT6-based architecture it's quite likely that using 5:3 or 6:3 compressors would be a better idea | 12:52 |
| *** indy has joined #yosys | 12:53 | |
| pepijndevos | hm yea you could not actually use ALU hardware for the full adders, because at least on gowin you can't access the carry chain in regular logic. | 12:54 |
| mwk | oh it doesn't | 12:54 |
| mwk | it only uses the carry chain *for the final stage* | 12:54 |
| mwk | the compression stages are just plain LUTs | 12:54 |
| pepijndevos | right | 12:54 |
| mwk | for gowin, being a LUT4 architecture, 3:2 compressors should actually be optimal | 12:56 |
| *** indy has quit IRC | 13:01 | |
| *** indy has joined #yosys | 13:08 | |
| *** indy has quit IRC | 13:21 | |
| *** indy has joined #yosys | 13:26 | |
| *** _whitelogger has quit IRC | 13:51 | |
| *** _whitelogger has joined #yosys | 13:53 | |
| *** indy has quit IRC | 14:14 | |
| *** indy has joined #yosys | 14:20 | |
| *** emeb has joined #yosys | 14:42 | |
| *** kristianpaul has quit IRC | 14:56 | |
| *** kristianpaul has joined #yosys | 15:02 | |
| *** jakobwenzel has quit IRC | 15:15 | |
| *** az0re has quit IRC | 15:39 | |
| *** kraiskil has joined #yosys | 15:45 | |
| *** kraiskil has quit IRC | 15:52 | |
| *** az0re has joined #yosys | 16:04 | |
| *** kraiskil has joined #yosys | 16:05 | |
| *** emeb_mac has joined #yosys | 16:46 | |
| *** emeb_mac has quit IRC | 16:57 | |
| *** citypw has quit IRC | 17:23 | |
| *** X-Scale has quit IRC | 17:49 | |
| *** X-Scale has joined #yosys | 17:55 | |
| *** kraiskil has quit IRC | 19:03 | |
| *** kraiskil has joined #yosys | 19:17 | |
| *** az0re has quit IRC | 19:22 | |
| *** az0re has joined #yosys | 19:35 | |
| *** kraiskil has quit IRC | 20:31 | |
| *** kristianpaul has quit IRC | 20:35 | |
| *** emeb_mac has joined #yosys | 20:36 | |
| *** kristianpaul has joined #yosys | 20:40 | |
| Lofty | Does anybody have any idea why Yosys might turn a fairly standard synchronous-read ROM into an asynchronous-read ROM? | 21:05 |
| Lofty | https://gist.github.com/sylefeb/452f6b97f493041fc341f42fc6682ecb#file-build1-v-L134-L136 | 21:05 |
| tpb | Title: build1.v · GitHub (at gist.github.com) | 21:05 |
| Lofty | This pattern looks correct to me, but memory_bram reports it being an async read port | 21:05 |
| daveshah | I think the truncation here is the problem: https://gist.github.com/sylefeb/452f6b97f493041fc341f42fc6682ecb#file-build1-v-L529 | 21:08 |
| tpb | Title: build1.v · GitHub (at gist.github.com) | 21:08 |
| daveshah | this is a known bug in memory_dff | 21:08 |
| daveshah | https://github.com/YosysHQ/yosys/issues/1854 | 21:09 |
| tpb | Title: memory_dff does not merge registers into read ports with unused bits · Issue #1854 · YosysHQ/yosys · GitHub (at github.com) | 21:09 |
| Lofty | Thank you, daveshah | 21:11 |
| *** emeb_mac has quit IRC | 21:18 | |
| *** emeb has quit IRC | 21:19 | |
| *** emeb_mac has joined #yosys | 21:19 | |
| *** emeb has joined #yosys | 21:20 | |
| *** tux3 has joined #yosys | 21:44 | |
| *** Asu has quit IRC | 21:44 | |
| *** emeb has quit IRC | 22:03 | |
| *** emeb has joined #yosys | 22:04 | |
| *** lf has quit IRC | 23:10 | |
| *** lf has joined #yosys | 23:10 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!