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| pepijndevos | glad to say I at least broke it myself... by changing the timing numbers it appears | 07:06 |
|---|---|---|
| pepijndevos | daveshah, any reason why increasing the delay of pips would fail routing? | 07:12 |
| daveshah | Assuming they aren't totally nonsensical, and in the same couple of orders of magnitude as the delay estimates, no | 07:13 |
| pepijndevos | if I do ctx.addPip with ctx.getDelayFromNS(0.05) it works great, but if I do it with 1.225 it fails to route | 07:13 |
| pepijndevos | I believe the 0.05 came from the upstream simple example | 07:15 |
| pepijndevos | 1.225 is a number I pulled from the critical path of the vendor tools | 07:15 |
| daveshah | You probably need to change the delay estimate scaling too | 07:19 |
| pepijndevos | the what? | 07:19 |
| daveshah | It needs to be in the same order of magnitude as the pip delays or the router won't know what to do | 07:19 |
| daveshah | https://github.com/YosysHQ/nextpnr/blob/master/docs/generic.md#void-setdelayscalingdouble-scale-double-offset | 07:20 |
| tpb | Title: nextpnr/generic.md at master · YosysHQ/nextpnr · GitHub (at github.com) | 07:20 |
| pepijndevos | uh, so how do I come up with reasonable numbers for that? | 07:22 |
| daveshah | They only need to be in the right order of magnitude | 07:23 |
| pepijndevos | So I just set both numbers equal to the pip delay? | 07:23 |
| daveshah | Saying, idk, 0.5ns for offset and 0.5ns for scale would probably be a place to start | 07:23 |
| pepijndevos | Alright. | 07:24 |
| pepijndevos | What I really need to do is document the fanout timing stuff | 07:24 |
| pepijndevos | jaaay works now | 07:27 |
| pepijndevos | as a temporary fix at least | 07:27 |
| daveshah | Incidentally, 1.225 seems like quite a high pip delay | 07:28 |
| daveshah | that's about the slowest pip in the up5k which is already a very slow FPGA | 07:29 |
| pepijndevos | yea... well... this was probably a conservative number used by their synthesis tools | 07:33 |
| pepijndevos | The slowest Gowin devices are... really slow | 07:33 |
| pepijndevos | I think it should be not too hard to get the actual answer from the vendor db | 07:35 |
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| pepijndevos | saaaaad... yosys qos is actually going backwords for picosoc on apicula | 09:01 |
| pepijndevos | I used to be able to just barely fit it, but now it takes 104% slices | 09:01 |
| Lofty | pepijndevos: how much does ABC9 help? :p | 09:59 |
| pepijndevos | Lofty, Apicula does not use the actual synth_gowin because of the generic nextpnr target | 10:32 |
| pepijndevos | Without the correct data, it's actually worse | 10:32 |
| pepijndevos | 115% | 10:32 |
| pepijndevos | Maybe it's time for a serv core :))) | 10:33 |
| pepijndevos | Or maybe it's time for a proper nextpnr target... | 10:36 |
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| jeanthom | good evening everyone! I'm running into an issue with my ECP5 DDR3 controller, and I can't figure what's wrong. | 18:38 |
| jeanthom | Using the same bitsteam, I get different burstdet values from the DQSBUFM | 18:39 |
| jeanthom | Burstdet looks like this when everything is fine: 01110011 | 18:39 |
| jeanthom | And randomly I get 00000111 and memtest fails | 18:40 |
| jeanthom | (the "00000111" thing is burstdet with different values of readclksel) | 18:40 |
| daveshah | Are you being careful to start things up correctly? | 18:47 |
| daveshah | https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/ecp5ddrphy.py#L56 | 18:47 |
| tpb | Title: litedram/ecp5ddrphy.py at master · enjoy-digital/litedram · GitHub (at github.com) | 18:47 |
| jeanthom | daveshah, yep my code is fairly similar to LiteDRAM | 18:58 |
| jeanthom | https://github.com/jeanthom/gram/blob/master/gram/phy/ecp5ddrphy.py#L25-L69 | 18:58 |
| tpb | Title: gram/ecp5ddrphy.py at master · jeanthom/gram · GitHub (at github.com) | 18:58 |
| daveshah | Yeah, that should be fine then | 18:59 |
| jeanthom | Also in simulation my read transactions are totally fine, but I don't get activity on burstdet (Lattice verilog models + Icarus Verilog) | 19:04 |
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| daveshah | Huh, not sure what is happening then | 19:22 |
| daveshah | I've definitely seen burstdet work in an iverilog simulation but it was a long time ago | 19:22 |
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| cr1901_modern | daveshah: Have you ever seen this warning? http://ix.io/2twl | 19:52 |
| daveshah | Yes it is because those functions are a bit long | 19:52 |
| cr1901_modern | Not sure when it started, but compiling baseconfigs.cc seems to have started taking a horrific amount of memory (5GB) | 19:52 |
| daveshah | They haven't changed for well over a year | 19:53 |
| cr1901_modern | Wonder if it's always been that way and I just noticed | 19:53 |
| daveshah | If it is causing a problem then ideally they should move into the chipdb instead | 19:53 |
| daveshah | It's not ideal but then that applies to a lot of nextpnr at the momen5 | 19:53 |
| cr1901_modern | Last time I built nextpnr-ecp5 was late June. I don't _recall_ anything like this happening. But no way to test now. | 19:54 |
| cr1901_modern | Anyways, I'll leave it be for now and let you know if I find anything. I could've very well just not noticed | 19:54 |
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| cr1901_modern | daveshah: Yea, I basically concluded that this always happened and I just didn't notice until today. Oops :P | 21:30 |
| daveshah | Maybe it is possible to set things up so that file is built with O0 | 21:31 |
| daveshah | That would probably help the compiler a bit | 21:31 |
| cr1901_modern | That's one option. If it becomes a bigger problem, I'll look into it | 21:32 |
| sorear | all fun and games until you hit an -O0 only compiler crash | 21:33 |
| whitequark | isn't that just some data? | 21:42 |
| whitequark | (also by definition -O0 compiler crashes are the easiest to debug, no?) | 21:43 |
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| mumptai | https://github.com/RasmusB/rbServo | 22:58 |
| tpb | Title: GitHub - RasmusB/rbServo: Hobby servo controller with CANBUS support (at github.com) | 22:58 |
| mumptai | sry, wrong window | 22:58 |
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