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| Lofty | Only in Verilog can you accidentally create numbers the universe does not have enough entropy to represent | 14:19 |
|---|---|---|
| Lofty | Well. Not "only" in Verilog, I suppose | 14:19 |
| Lofty | But still | 14:19 |
| whitequark | Lofty: https://nmigen.info/nmigen/latest/lang.html#lang-hugeshift | 14:25 |
| tpb | Title: Language guide nMigen toolchain 0.3.dev143 documentation (at nmigen.info) | 14:25 |
| Lofty | whitequark: I'm pretty sure pysim will also break on a 208GiB Signal | 14:30 |
| whitequark | not necessarily, actually | 14:32 |
| whitequark | as long as you only use the low bits i think it might be f... ah no | 14:32 |
| whitequark | the mask will be that long | 14:32 |
| whitequark | it will | 14:32 |
| Lofty | So nMigen probably also has some point where it can't feasibly represent some signals. | 14:35 |
| whitequark | yep | 14:36 |
| whitequark | it already rejects signals over 16 Mbits in back.rtlil | 14:36 |
| whitequark | Verilog only requires support for 64 Kbits, and Yosys flat out breaks on 4 Gbits (the lexer has UB at that point) | 14:36 |
| whitequark | (or had, I might have fixed it) | 14:36 |
| whitequark | I'm gonna lower that to 1 Mbit, I think | 14:37 |
| daveshah | I would suggest a 64kbit limit for now | 14:37 |
| whitequark | daveshah: thanks, will do | 14:37 |
| daveshah | iirc even 128kbit ish was killing performance in some cases | 14:37 |
| whitequark | oh yeah I misremembered | 14:42 |
| whitequark | hm, wait | 14:43 |
| mwk | hmm | 14:44 |
| mwk | how are things like memory init values handled? | 14:45 |
| mwk | these could very reasonably grow Big | 14:45 |
| whitequark | in yosys or? | 14:45 |
| daveshah | oh yeah, hmm | 14:45 |
| mwk | nmigen | 14:45 |
| whitequark | nmigen emits a single $meminit cell with \DATA connected immediately to a constant | 14:46 |
| whitequark | so no wires there | 14:46 |
| mwk | alright, good enough then | 14:47 |
| mwk | (for nmigen at least; yosys still make a SigSpec out of it, hmmmm) | 14:48 |
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| mwk | how are $meminit with non-const ADDR / DATA useful? | 14:50 |
| whitequark | mwk: lets you do things like mem[0] = 1+1; | 14:51 |
| whitequark | without having to evaluate it in the frontend, i gess | 14:51 |
| mwk | oh, hm | 14:51 |
| mwk | but doesn't the frontend already have to know how to evaluate const expressions for things like cell parameters anyway? | 14:57 |
| whitequark | no idea | 14:57 |
| daveshah | yeah, it does | 14:58 |
| daveshah | also for things like wire widths | 14:58 |
| mwk | ... petition to change it to parameters instead of ports during memory inference redesign? | 15:00 |
| daveshah | don't have an immediate objection but there may be a subtlety I'm missing | 15:00 |
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| emeb | Am I missing something or are the ECP5 PLLs and other clock management cells not yet supported by yosys? | 18:36 |
| daveshah | ? | 18:36 |
| daveshah | They are supported fine | 18:36 |
| emeb | Looking through cells_sim.v I don't see the instantiation templates. | 18:37 |
| daveshah | They are in cells_bb.v | 18:37 |
| emeb | thx | 18:37 |
| Lofty | daveshah: are PLLs actually simulatable? | 19:00 |
| Lofty | It seems difficult to model (to me) | 19:00 |
| emeb | It can be done, but it's usually a hack in verilog. I've done it by making a behavioral model of what a PLL does, but it's really hard to match the actual loop dynamics. | 19:16 |
| emeb | Hmm... when I try to instantiate the EHXPLL yosys is happy and nextpnr seems fine through most of the process but then throws an assertion during routing. | 19:18 |
| emeb | Terminate called after throwing an instance of 'nextpnr_ecp5::assertion_failure' | 19:19 |
| emeb | what(): Assertion failure: is_string (/home/ericb/build/trellis/nextpnr/common/nextpnr.h:362) | 19:19 |
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