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| Forty-Bot | why is /r/yosys submission restricted? | 11:05 |
|---|---|---|
| Lofty | Given the only mod on there is Claire, she probably doesn't want to deal with it | 11:06 |
| Forty-Bot | why not get more mods? | 11:06 |
| Forty-Bot | or at least pin a post saying why it's closed | 11:06 |
| Lofty | Claire's not here | 11:06 |
| Lofty | So, the question is kinda pointless | 11:06 |
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| ZipCPU | It's restricted? I wasn't aware of that | 12:52 |
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| Forty-Bot | ZipCPU: yeah, I only noticed because I thought it was fishy that there had been no posts for 2 months | 16:18 |
| ZipCPU | Well, okay, cool, I'll stop checking there for posts to answer ;) | 16:22 |
| ZipCPU | I'm guessing their plan was to switch to stack overflow for user help requests | 16:23 |
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| jmamish | I've been checking my designs by synthesizing (for ice40) with yosys, then dumping a synthesized version of my design with "write_verilog". I then run both my RTL design and the synthesized design in iverilog and compare results. | 22:50 |
| jmamish | I've been checking my designs by synthesizing (for ice40) with yosys, then dumping a synthesized version of my design with "write_verilog". I then run both my RTL design and the synthesized design in iverilog and compare results. | 22:50 |
| jmamish | This has helped me find a few dumb bugs, but it's obviously really really slow in iverilog (takes like 50 - 100x as long as the RTL design). | 22:51 |
| jmamish | Is it pointless to run verilator instead on the synthesized design, or can I use verilator to speed up simulation of the synthesized design? | 22:51 |
| whitequark | verilator should speed it up | 22:51 |
| whitequark | you could use cxxrtl as well | 22:51 |
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