Friday, 2020-07-17

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matthuszaghHello. I'm attempting to synthesize a xilinx 7-series design with yosys. However, the synth_xilinx command gives the error "Conflicting initialization values for \i". In the verilog file it complains about, I declare `integer i;` once, and then use it several times for different for loops. Some of these loops initialize `i` with `i=0` and some initialize it with `i=1`. Is this what yosys is complaining about?18:53
LoftyI think you want `genvar i`, not `integer i`18:53
matthuszaghLofty: ah, ok. I thought genvar was only for generate blocks, is that incorrect?18:54
LoftyIn Verilog (2005?) `for` at the top level of a module == `generate for`18:54
LoftyIn other words: you already have a generate block18:55
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matthuszaghOh good to know, thanks. I will try genvar then18:55
LoftyYosys is generally a bit stricter to the standard than other compilers18:55
LoftyBut its error messages are...not the best18:56
matthuszaghHm now I'm getting "Left hand side of 1st expression of generate for-loop is not a register!"18:57
matthuszaghfor18:57
matthuszagh18:57
matthuszagh   reg signed [INPUT_WIDTH-1:0]         shift_reg [0:M-2];18:57
matthuszagh   genvar                               i;18:57
matthuszagh   initial for (i=0; i<M-1; i=i+1) shift_reg[i] = {INPUT_WIDTH{1'b0}};18:57
matthuszaghIt should be though. I only use `shift_reg` in clocked always blocks19:00
LoftyI checked the standard; yes, it should be `genvar`.19:00
matthuszaghLofty: thanks for checking that. Mind pointing me to the page?19:00
matthuszaghtrying to get better at going straight to the standard for this sort of stuff, but still a bit inefficient at reading it/finding things19:01
Loftymatthuszagh: IEEE 1364-2005 page 183: "The loop index variable shall be declared in a genvar declaration prior to its use in a loop generate scheme."19:03
LoftyAre you using `i` in multiple loops?19:03
matthuszaghterrific, thanks19:04
matthuszaghyes19:04
LoftyNo nested loops with `i` as the same variable, right?19:06
Lofty(the standard forbids that)19:06
matthuszaghCorrect, they're separate.19:06
LoftyWhat happens if you run Verilator on your code?19:07
Lofty(as in, `verilator --lint-only -Wall`19:07
Lofty)19:07
matthuszaghgood question, lemme try19:07
matthuszaghGenvar not legal in non-generate for (IEEE 1800-2017 27.4)19:08
matthuszaghSuggest move for loop upwards to generate-level scope19:08
matthuszaghinitial for (i=0; i<M-1; i=i+1) shift_reg[i] = {INPUT_WIDTH{1'b0}};19:08
matthuszaghthen also19:08
matthuszaghGenvar not legal in non-generate for19:08
LoftyVerilator's using a much later standard than Yosys there :P19:08
matthuszaghthere's no way to set the standard to 2005 is there?19:09
Loftyverilator --language 1364-200519:10
LoftyThat matches what Yosys (presently) supports19:10
matthuszaghgreat19:11
matthuszaghok basically the same errors19:11
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matthuszaghso it sounds like i have to write generate explicitly?19:12
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LoftyProbably; I'll admit to not being a language lawyer19:12
matthuszaghno worries, i'll try that out19:15
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matthuszaghalso strangely, the language verilator flag doesn't seem to be doing much for me19:15
matthuszaghit still complains about 1800-2017 issues19:16
LoftyMaybe the error messages are hardcoded there19:16
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matthuszaghI noticed in the yosys manual (2.2.5) it says for loops are supported in always blocks and in generate statements at the module level19:59
matthuszaghthis doesn't say anything about initial blocks19:59
matthuszaghalso, the arrays and memories section (2.2.6) uses integer rather than genvar for the for-loop index20:00
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matthuszaghDoes every memory assignment/initialization for loop need its own `integer`? I get an error for conflicting initialization values unless I do this.22:00
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