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| matthuszagh | Hello. I'm attempting to synthesize a xilinx 7-series design with yosys. However, the synth_xilinx command gives the error "Conflicting initialization values for \i". In the verilog file it complains about, I declare `integer i;` once, and then use it several times for different for loops. Some of these loops initialize `i` with `i=0` and some initialize it with `i=1`. Is this what yosys is complaining about? | 18:53 |
|---|---|---|
| Lofty | I think you want `genvar i`, not `integer i` | 18:53 |
| matthuszagh | Lofty: ah, ok. I thought genvar was only for generate blocks, is that incorrect? | 18:54 |
| Lofty | In Verilog (2005?) `for` at the top level of a module == `generate for` | 18:54 |
| Lofty | In other words: you already have a generate block | 18:55 |
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| matthuszagh | Oh good to know, thanks. I will try genvar then | 18:55 |
| Lofty | Yosys is generally a bit stricter to the standard than other compilers | 18:55 |
| Lofty | But its error messages are...not the best | 18:56 |
| matthuszagh | Hm now I'm getting "Left hand side of 1st expression of generate for-loop is not a register!" | 18:57 |
| matthuszagh | for | 18:57 |
| matthuszagh | 18:57 | |
| matthuszagh | reg signed [INPUT_WIDTH-1:0] shift_reg [0:M-2]; | 18:57 |
| matthuszagh | genvar i; | 18:57 |
| matthuszagh | initial for (i=0; i<M-1; i=i+1) shift_reg[i] = {INPUT_WIDTH{1'b0}}; | 18:57 |
| matthuszagh | It should be though. I only use `shift_reg` in clocked always blocks | 19:00 |
| Lofty | I checked the standard; yes, it should be `genvar`. | 19:00 |
| matthuszagh | Lofty: thanks for checking that. Mind pointing me to the page? | 19:00 |
| matthuszagh | trying to get better at going straight to the standard for this sort of stuff, but still a bit inefficient at reading it/finding things | 19:01 |
| Lofty | matthuszagh: IEEE 1364-2005 page 183: "The loop index variable shall be declared in a genvar declaration prior to its use in a loop generate scheme." | 19:03 |
| Lofty | Are you using `i` in multiple loops? | 19:03 |
| matthuszagh | terrific, thanks | 19:04 |
| matthuszagh | yes | 19:04 |
| Lofty | No nested loops with `i` as the same variable, right? | 19:06 |
| Lofty | (the standard forbids that) | 19:06 |
| matthuszagh | Correct, they're separate. | 19:06 |
| Lofty | What happens if you run Verilator on your code? | 19:07 |
| Lofty | (as in, `verilator --lint-only -Wall` | 19:07 |
| Lofty | ) | 19:07 |
| matthuszagh | good question, lemme try | 19:07 |
| matthuszagh | Genvar not legal in non-generate for (IEEE 1800-2017 27.4) | 19:08 |
| matthuszagh | Suggest move for loop upwards to generate-level scope | 19:08 |
| matthuszagh | initial for (i=0; i<M-1; i=i+1) shift_reg[i] = {INPUT_WIDTH{1'b0}}; | 19:08 |
| matthuszagh | then also | 19:08 |
| matthuszagh | Genvar not legal in non-generate for | 19:08 |
| Lofty | Verilator's using a much later standard than Yosys there :P | 19:08 |
| matthuszagh | there's no way to set the standard to 2005 is there? | 19:09 |
| Lofty | verilator --language 1364-2005 | 19:10 |
| Lofty | That matches what Yosys (presently) supports | 19:10 |
| matthuszagh | great | 19:11 |
| matthuszagh | ok basically the same errors | 19:11 |
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| matthuszagh | so it sounds like i have to write generate explicitly? | 19:12 |
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| Lofty | Probably; I'll admit to not being a language lawyer | 19:12 |
| matthuszagh | no worries, i'll try that out | 19:15 |
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| matthuszagh | also strangely, the language verilator flag doesn't seem to be doing much for me | 19:15 |
| matthuszagh | it still complains about 1800-2017 issues | 19:16 |
| Lofty | Maybe the error messages are hardcoded there | 19:16 |
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| matthuszagh | I noticed in the yosys manual (2.2.5) it says for loops are supported in always blocks and in generate statements at the module level | 19:59 |
| matthuszagh | this doesn't say anything about initial blocks | 19:59 |
| matthuszagh | also, the arrays and memories section (2.2.6) uses integer rather than genvar for the for-loop index | 20:00 |
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| matthuszagh | Does every memory assignment/initialization for loop need its own `integer`? I get an error for conflicting initialization values unless I do this. | 22:00 |
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