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| thardin | I'm trying to optimize my sine module and yosys is turning my bram into LCs when I invert outputs for 180°-360° | 10:33 |
|---|---|---|
| daveshah | Is the inversion added before the output register by any chance? | 10:34 |
| daveshah | Yosys won't retime that away | 10:34 |
| thardin | removing the inversion, so that the output is abs(sin(x)) keeps the bram | 10:34 |
| thardin | here's an excerpt: | 10:34 |
| thardin | wire [SINE_BITS-1:0] lut = sine_lut[xlow[SINE_SZ-2:SINE_SZ-LUT_SZ-1]]; | 10:34 |
| thardin | assign y = lut ^ (x[SINE_SZ-1] ? 65535 : 0); | 10:34 |
| thardin | where y is the output wire | 10:34 |
| thardin | ah is there a case where a fake temporary reg is needed? | 10:34 |
| thardin | s/there/this/ | 10:35 |
| daveshah | Yes if you want this to map to BRAM then lut needs to be a reg | 10:37 |
| thardin | hmm | 10:37 |
| daveshah | clocked by the read clock | 10:37 |
| thardin | I can't use bram as a combinatoric LUT? | 10:37 |
| daveshah | No | 10:37 |
| thardin | sad | 10:37 |
| daveshah | If it worked before it was because Yosys was folding in a register from somewhere else | 10:38 |
| daveshah | which it can't do with the inversion | 10:38 |
| thardin | can't imagine why I couldn't put combinatorics after the output of the bram, but maybe with the surrounding context it becomes impossible | 10:38 |
| daveshah | You can do | 10:39 |
| daveshah | so long as that output is clocked | 10:39 |
| thardin | it is, but in another module. maybe yosys isn't able to see that | 10:40 |
| daveshah | It will be able to see that if there is no logic in between | 10:41 |
| thardin | aha | 10:41 |
| thardin | that explains it :) | 10:41 |
| thardin | is this a limitation in yosys or verilog? or both? | 10:42 |
| daveshah | In general synthesis tools don't like moving logic around registers | 10:42 |
| daveshah | this is usually opt-in as a retiming option, but even then that is to improve perfomance not help extract memories in more cases | 10:43 |
| thardin | right, I was about to say | 10:43 |
| thardin | this kind of construct would degrade performance | 10:43 |
| thardin | and I have plenty of "cycles" available in my little state machine to pipeline things | 10:44 |
| thardin | not that my current ADCs and DACs are anywhere near fast enough to exploit this. yet. | 10:46 |
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| thardin | hooray, it works | 11:22 |
| Lofty | <daveshah> In general synthesis tools don't like moving logic around registers <-- unless you're Quartus, anyway | 11:26 |
| daveshah | Retiming is enabled-by-default? | 11:27 |
| Lofty | Yep | 11:27 |
| Lofty | Though I'm pretty sure it's performed in place and route | 11:28 |
| thardin | quadrupled the accuracy of it too | 11:39 |
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