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| pepijndevos | oh nooo, I'm doing something silly | 16:59 |
|---|---|---|
| pepijndevos | Traceback (most recent call last): | 16:59 |
| pepijndevos | File "/home/pepijn/code/nextpnr/ecp5/trellis_import.py", line 22, in <module> | 16:59 |
| pepijndevos | import database | 16:59 |
| pepijndevos | ModuleNotFoundError: No module named 'database' | 16:59 |
| pepijndevos | why is it trying to use prjtrellis from my home dir? | 16:59 |
| daveshah | It isn't, that's the path to the file in nextpnr | 17:09 |
| daveshah | make sure TRELLIS_INSTALL_PREFIX is being passed to cmake | 17:10 |
| pepijndevos | yay | 17:20 |
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| thardin | is it possible to do preprocessor-y things with yosys? | 18:16 |
| thardin | like -DFEATURE_X=1 | 18:16 |
| thardin | I have a design that works slightly different on artix-7 and ice40. would be nice to be able to build the same code for both | 18:16 |
| Lofty | thardin: add a space between the -D and the define | 18:24 |
| Lofty | But yeah, `read_verilog -D FOO=1` works | 18:24 |
| Lofty | And you can also pass it with `yosys -D FOO=1` | 18:25 |
| thardin | that's not what the manpage for -D says | 18:26 |
| thardin | -D <header_id>[:<filename>] dump the design when printing the specified log header to a file. yosys_dump_<header_id>.il is used as filename if none is specified. Use 'ALL' as <header_id> to dump at every header. | 18:26 |
| thardin | but now I see "help read_verilog" shows what you say. thanks, I should have thought of checking there too | 18:27 |
| Lofty | -D <macro>[=<value>] | 18:27 |
| Lofty | set the specified Verilog define (via "read -define") | 18:27 |
| Lofty | (for `yosys -D`) | 18:27 |
| Lofty | -Dname[=definition] | 18:27 |
| Lofty | define the preprocessor symbol 'name' and set its optional value | 18:27 |
| Lofty | 'definition' | 18:27 |
| Lofty | (for `read_verilog -D`) | 18:27 |
| thardin | strange | 18:28 |
| thardin | this is with Yosys 0.9+1706 (git sha1 a0cc795e, gcc 6.3.1 -fPIC -Os) | 18:28 |
| Lofty | `yosys -h` | 18:28 |
| Lofty | It's near the bottom | 18:28 |
| thardin | uhhh | 18:29 |
| thardin | so | 18:29 |
| thardin | the manpage and --help don't agree | 18:29 |
| Lofty | Yosys does not have a manpage | 18:29 |
| thardin | I can "man yosys" just fine | 18:29 |
| Lofty | I can't | 18:29 |
| Lofty | There is no manual page in the Yosys source that I can find | 18:30 |
| daveshah | Yeah I don't seem to have one either | 18:31 |
| daveshah | must be some distro-provided thing or something | 18:31 |
| thardin | I was just about to say | 18:32 |
| thardin | I installed debian's version but then compiled my own | 18:32 |
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| Lofty | Does anybody know of a hack to obtain a unique identifier - or even just the cell name - in techmap? | 21:09 |
| Lofty | For context: Quartus wants a "logical RAM name" in the memory cells | 21:09 |
| Lofty | I initially set this to be a constant string and assumed Quartus would be smart enough | 21:10 |
| Lofty | But no, it wants a unique identifier | 21:11 |
| Lofty | And the only alternative I can think of is manually fiddling with RTLIL for this | 21:12 |
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