Saturday, 2020-07-11

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pepijndevosoh nooo, I'm doing something silly16:59
pepijndevosTraceback (most recent call last):16:59
pepijndevos  File "/home/pepijn/code/nextpnr/ecp5/trellis_import.py", line 22, in <module>16:59
pepijndevos    import database16:59
pepijndevosModuleNotFoundError: No module named 'database'16:59
pepijndevoswhy is it trying to use prjtrellis from my home dir?16:59
daveshahIt isn't, that's the path to the file in nextpnr17:09
daveshahmake sure TRELLIS_INSTALL_PREFIX is being passed to cmake17:10
pepijndevosyay17:20
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thardinis it possible to do preprocessor-y things with yosys?18:16
thardinlike -DFEATURE_X=118:16
thardinI have a design that works slightly different on artix-7 and ice40. would be nice to be able to build the same code for both18:16
Loftythardin: add a space between the -D and the define18:24
LoftyBut yeah, `read_verilog -D FOO=1` works18:24
LoftyAnd you can also pass it with `yosys -D FOO=1`18:25
thardinthat's not what the manpage for -D says18:26
thardin-D <header_id>[:<filename>] dump  the  design  when printing the specified log header to a file.  yosys_dump_<header_id>.il is used as filename if none is specified. Use 'ALL' as <header_id> to dump at every header.18:26
thardinbut now I see "help read_verilog" shows what you say. thanks, I should have thought of checking there too18:27
Lofty    -D <macro>[=<value>]18:27
Lofty        set the specified Verilog define (via "read -define")18:27
Lofty(for `yosys -D`)18:27
Lofty    -Dname[=definition]18:27
Lofty        define the preprocessor symbol 'name' and set its optional value18:27
Lofty        'definition'18:27
Lofty(for `read_verilog -D`)18:27
thardinstrange18:28
thardinthis is with Yosys 0.9+1706 (git sha1 a0cc795e, gcc 6.3.1 -fPIC -Os)18:28
Lofty`yosys -h`18:28
LoftyIt's near the bottom18:28
thardinuhhh18:29
thardinso18:29
thardinthe manpage and --help don't agree18:29
LoftyYosys does not have a manpage18:29
thardinI can "man yosys" just fine18:29
LoftyI can't18:29
LoftyThere is no manual page in the Yosys source that I can find18:30
daveshahYeah I don't seem to have one either18:31
daveshahmust be some distro-provided thing or something18:31
thardinI was just about to say18:32
thardinI installed debian's version but then compiled my own18:32
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LoftyDoes anybody know of a hack to obtain a unique identifier - or even just the cell name - in techmap?21:09
LoftyFor context: Quartus wants a "logical RAM name" in the memory cells21:09
LoftyI initially set this to be a constant string and assumed Quartus would be smart enough21:10
LoftyBut no, it wants a unique identifier21:11
LoftyAnd the only alternative I can think of is manually fiddling with RTLIL for this21:12
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