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| az0re | Can someone please explain to me exactly what the `-g` option to `abc` does? | 01:03 |
|---|---|---|
| az0re | I am not trying to do LUT mapping; I just want to use ABC for some logic optimization. But after I export the circuit to ABC and it gets re-integrated, I only get a bunch of `$lut` cells. If I `techmap` this circuit, I get a bunch of $_MUX_ cells. | 01:04 |
| az0re | I would like to have it re-map basic gates: AND, OR, MUX, etc. That's not what `-g` does? | 01:05 |
| mwk | az0re: just don't pass any -lut* option to abc and it'll map to gates instead | 01:09 |
| az0re | That's not my experience | 01:16 |
| az0re | mwk: If I just do `abc -script +[...] mymodule` I get a bunch of $lut cells | 01:17 |
| az0re | I actually have some LUT comprehension code I could add to turn LUTs from ABC back into gates, but I am confused, as it seems like `-g` should do that already. | 01:18 |
| mwk | what's the full yosys script you're using? | 01:19 |
| az0re | See PR #2019, file examples/smtbmc/glift/alu2.ys | 01:19 |
| az0re | https://github.com/YosysHQ/yosys/pull/2019/files#diff-1135813b7bf0e2e6e7c4d02ae75e36d4 | 01:20 |
| tpb | Title: Add `glift` command for creating gate-level information flow tracking models and optimization problems by boqwxp · Pull Request #2019 · YosysHQ/yosys · GitHub (at github.com) | 01:20 |
| az0re | abc -script +print_stats;strash;print_stats;drwsat;print_stats;print_stats;fraig;print_stats;dc2,-l,-b;print_stats;irw,-l,-z;print_stats;refactor,-N,15,-z;print_stats;dch,-S,50000,-C,10000;print_stats;dc2,-l;print_stats;fraig,-C,10000;print_stats miter | 01:21 |
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| az0re | FWIW I see a ~4x solver speedup recovering ANDs from the LUTs instead of relying on a stupid MUX tree, so it's important to me to get a reasonable AIG back instead of LUTs | 01:23 |
| az0re | (I suspect XOR recovery would give a speedup, too, but finding XOR-isomorphic 2-feasible cuts in the AIG is another task for another day...) | 01:25 |
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| mwk | az0re: well your abc script doesn't actually do any technology mapping to the yosys cells | 01:40 |
| mwk | hence abc itself outputs LUTs | 01:40 |
| az0re | Aha. What am I missing? | 01:41 |
| az0re | Never done techmapping with ABC before | 01:41 |
| mwk | &nf is what does the trick | 01:42 |
| az0re | Orly | 01:43 |
| az0re | Thanks :) | 01:43 |
| az0re | Oh Alan, how in the world should I hypothesize what &nf should do? | 01:44 |
| az0re | ... | 01:44 |
| mwk | basically appending ';&get,-n;&dch,-f;&nf;&put' to your script makes it work | 01:46 |
| mwk | because the design needs to be put into &-space to be techmapped, whatever the fuck it is | 01:46 |
| az0re | lol totally absurd | 01:47 |
| az0re | Thanks for the tip, you probably saved me 3 hours or something | 01:48 |
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| whitequark | &-space | 01:58 |
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| az0re | A problem that took 60s to solve is now solved in 6s. Rad. Thanks, mwk. | 02:28 |
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| az0re | Does anyone have experience with PerformanceTimer ? I'm trying to use it in a very simple way but it's giving me erroneous timing info. 3m40s of wall clock time is reported as 0.05s | 04:29 |
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| az0re | I also tried not using begin(), end(), and sec(), and calling PerformanceTimer::query() directly, but it also does not seem to work... A few seconds is reported as 0.02s, and a few minutes as 0.035s | 04:44 |
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| az0re | Strangely, the time reporting when I exit Yosys is mostly reasonable, with some stats in the seconds | 04:45 |
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| Lofty | I think &-space is XAIG. | 09:09 |
| Lofty | At least, ABC9 transformations are all prefixed by & and I think those use XAIG. | 09:10 |
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