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| Lofty | ABC can take latches as input, right? | 16:43 |
|---|---|---|
| daveshah | I _think_ what abc call latches are actually flip-flops | 16:46 |
| daveshah | Maybe it supports real latches too though | 16:47 |
| Lofty | I was looking at the QuickLogic code and wondering if it would be more efficient to let ABC attempt to pack logic into latches | 16:47 |
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| mwk | Lofty: huh? | 16:48 |
| mwk | what do you mean by logic into latches? | 16:48 |
| Lofty | Imagine you have, say, a cone of logic with a latch and some other logic that fits inside a LUT | 16:49 |
| Lofty | What the QL flow does is map the latch manually | 16:50 |
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| Lofty | Whereas the mapper could pack some of the logic into the LUT, reducing area | 16:50 |
| mwk | oh, like map latch into a LUT | 16:50 |
| mwk | that's a much more generic issue than just quicklogic though | 16:50 |
| mwk | like half our targets don't really support latches and they end up as logic | 16:51 |
| Lofty | That's why I asked if ABC could do it | 16:51 |
| Lofty | intel_alm doesn't presently map latches at all :P | 16:51 |
| mwk | which tbh I'd like to get rid of (as in, get rid of the current per-target way), and handle it in dfflegalize | 16:51 |
| Lofty | Sure | 16:51 |
| mwk | anyway I thought you were asking about something else with "pack logic into latches" | 16:52 |
| mwk | Xilinx has a fun mode where you can use a latch as an AND gate or as an OR gate | 16:52 |
| Lofty | Mmm | 16:53 |
| mwk | (which is of course very tricky to use efficiently because it involves turning *all* FFs in a slice into AND/OR gates, and good luck teaching synthesis to notice cases where it's worth it) | 16:54 |
| mwk | also I'm going to take a guess the timings for that gate are kinda shit | 16:55 |
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| Lofty | Mmm | 17:00 |
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| tnt | So, can a (*whitebox*) module be top-level ? If I read_verilog one and then try 'show' it says "Nothing to show". If I remove the (*whitebox*) attrbiute, it works fine. | 18:57 |
| tnt | ok, bad example, 'show' fails on the working machine with the old yosys. | 18:59 |
| tnt | The real command is 'read_verilog ./symbiflow-arch-defs/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select F1 %co* o:* %i F1 %d' | 19:00 |
| tnt | which works on an "older" yosys (with the (*whitebox*) attr on F_FRAG module) and doesn't on a newer yosys ( I have to remove the whitebox attr ) | 19:01 |
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