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| asinghan1 | hwllo | 02:01 |
|---|---|---|
| asinghan1 | I'm trying to synthesize for an ECP5 | 02:01 |
| asinghan1 | And I'm having the issue where when I create a design with a block RAM with 9-bit width and 2048-bit depth, everything works fine | 02:01 |
| asinghan1 | but if i increase it to 9-bit width and 4096-bit depth, yosys suddenly decides to use distributed RAMs instead of BRAMs | 02:02 |
| asinghan1 | with everything else remaining the same | 02:02 |
| az0re | I guess this is yet another memory inference problem | 02:02 |
| asinghan1 | (the 9-bit width and 4096-bit depth would require 2 block RAMs in the cascaded configuration, is there no way to infer the cascaded config?) | 02:02 |
| asinghan1 | Do I just need to instantiate multiple memories and MUX between them in my BRAM wrapper? | 02:03 |
| az0re | I'm sorry, I don't really know enough about this part of Yosys to help you, but I think others like @whitequark and @mwk might know more (though you will need to be patient). | 02:03 |
| az0re | > Do I just need to instantiate multiple memories and MUX between them in my BRAM wrapper? | 02:03 |
| az0re | From my ignorant position, I say: Try it. Sounds like it should work to me. | 02:04 |
| az0re | Maybe the ideal solution is to have it done automatically, but as a workaround to get your design working now, try it. | 02:04 |
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| corecode | awygle: yea, it's still quite some work | 06:16 |
| daveshah | 9 bit width and 4096 depth should definitely map to multiple BRAM automatically | 06:26 |
| daveshah | I've done similar things many times, something else must be going on that's stopping it from mapping | 06:27 |
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| jeanthom | Hi everyone! Does anyone know if you can use tristate signals in cxxrtl? | 12:24 |
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| ZirconiumX | jeanthom: In what context? | 12:41 |
| ZirconiumX | I'm fairly sure if Yosys understands it cxxrtl can translate it, but the expert on it would be whitequark herself | 12:42 |
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| jeanthom | ZirconiumX, I'm working on a "VirtualLatticeECP5Platform" for nMigen that uses CXXRTL instead of nextpnr. The goal here is to be able to emulate nMigen code that uses platform.request() | 12:46 |
| ZirconiumX | Mmm. That's the wrong approach, IMO | 12:48 |
| jeanthom | I got a PoC working (I can emulate LambdaSoC on it and get uart I/O) but I wanted to make sure that cxxrtl "officially" supports bi-directionnal signals (say for SD card emulation) | 12:48 |
| ZirconiumX | CXXRTL - AFAIK - is considered entirely the wrong approach | 12:48 |
| ZirconiumX | ..... | 12:49 |
| ZirconiumX | I'm brainfarting today | 12:49 |
| ZirconiumX | Please excuse me | 12:49 |
| ZirconiumX | "CXXRTL is considered entirely a different platform" | 12:49 |
| ZirconiumX | Additionally, "bidirectional" - AKA inouts - are supported fine by Yosys, but "tristate" issues warnings | 12:50 |
| ZirconiumX | If you want to simulate an SD card, don't do it by simulating how a particular FPGA simulates an SD card | 12:51 |
| ZirconiumX | jeanthom: ^ | 12:53 |
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| jeanthom | ZirconiumX, What do you mean by "a different platform"? I know that by doing it this way my emulation will be far from being accurate (no timing emulation, etc.) but I thought it would be sufficient for doing basic things. | 12:57 |
| ZirconiumX | nMigen has platforms, right? That gets passed as the platform argument to elaborate() | 12:58 |
| jeanthom | yup | 12:58 |
| ZirconiumX | So, instead of trying to emulate an ECP5's approach to doing things, just emulate the actual object somebody requests | 12:59 |
| ZirconiumX | When the user asks for an SD card, they're not asking for how an ECP5 does an SD card. | 12:59 |
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| whitequark | jeanthom: yeah what ZirconiumX says is correct | 17:01 |
| whitequark | I don't foresee adding a Virtual* platform for every existing platform | 17:01 |
| whitequark | if we do end up with platform simulations upstream (we probably will; #113) then it will happen without having to change user code | 17:01 |
| ZirconiumX | yay | 17:02 |
| whitequark | probably by adding another file generated by the build process or something like that, I'd have to think about it | 17:02 |
| whitequark | jeanthom: also regarding tristate signals, you cannot use tristate signals in cxxrtl as it has no concept of 'z | 17:02 |
| whitequark | and it is unlikely that it ever will, wires driven from multiple processes or assignments are a really bad fit for its architecture | 17:03 |
| jeanthom | whitequark, thanks for your reply. My virtual platform wasn't meant to be upstreamed, it was just a PoC that I would have used for basic nmigen tutorials | 17:09 |
| whitequark | I mean, people are asking for platform simulations, so it's probably better to have something that works for everyone | 17:10 |
| whitequark | if we're going to have it at all | 17:10 |
| whitequark | by tutorials, do you mean using CXXRTL to integrate a simulation with a simple GUI? | 17:10 |
| jeanthom | whitequark, yup | 17:11 |
| whitequark | cool! is there a reason you're using ECP5 specifically? | 17:12 |
| whitequark | platform.request() doesn't actually have to use tristate IO | 17:12 |
| jeanthom | whitequark, https://i.imgur.com/VjcGSrX.gif | 17:12 |
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| whitequark | it gives to the nmigen code a triple of (i,o,oe) which cxxrtl is perfectly fine with, so those signals could be added as toplevel ports | 17:12 |
| whitequark | is it just to reuse the ECPIX-5 board definition? | 17:12 |
| jeanthom | I'm working on some example code/tutorials for ECPIX-5 and I thought that having a simulator would be cool (not sure about the usefulness :D) | 17:13 |
| whitequark | ahh I see, yeah I do think it is quite cool! | 17:13 |
| jeanthom | using the original board definition with few modifications was a goal of mine, I know someone who spent countless hours debugging gateware because they used PinsN instead of Pins in their gateware, and it wasn't visible in their simulation :) | 17:15 |
| whitequark | hm yeah that's an issue | 17:16 |
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