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| awygle | i think the ice40 version of nextpnr actually builds slower than the ecp5 version | 04:22 |
|---|---|---|
| awygle | ... i also think it just caused clang to get oom-killed by buildling 8 chipdb files at once | 04:23 |
| whitequark | yes | 04:29 |
| whitequark | there's a flag to make it not do that | 04:30 |
| awygle | i just ran -j4 instead | 04:32 |
| awygle | but that's good to know | 04:32 |
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| bouliiii | hello there, I am considering buying a TinyFGPAEx from here: https://www.crowdsupply.com/tinyfpga/tinyfpga-ex. It looks the DRAM is a "HyperRam" and the refresh cycles look to be handled by the chip itself. Are they easy to program on the user side? Did any of you already program the TinyFPGAEx with Yosys? | 12:31 |
| dkozel | bouliiii: The TinyFPGA EX isn't for sale yet (as far as I know) | 12:34 |
| dkozel | I've been eagerly waiting for it | 12:34 |
| tnt | I wouldn't hold my breath. | 12:37 |
| dkozel | Sadly. It's still the ECP5 board I'm most interested in. | 12:39 |
| dkozel | Followed by an m.2 one | 12:39 |
| bouliiii | dkozel: Ah yes, you are right. I was confused by the ULX3S which does have a date now (august 2020). | 12:39 |
| tnt | But as for your original question, hyperram is about as easy as you can get for a modern RAM interface with a decent bandwidth. Not crazy like DDR3 but you still need to pay attention and play with the capture data phases. | 12:40 |
| bouliiii | tnt: thanks! | 12:41 |
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| ZirconiumX | az0re: You're boqwxp on GitHub, right? | 14:32 |
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