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| mithro | What is the magic sequence which tells verilog to not magically invent new variables -- something like `\`default_nettype none` ? | 01:42 |
|---|---|---|
| mithro | Looks like it is exactly "`default_nettype none"? | 01:43 |
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| ZipCPU | mithro: Yes, that's it: `default_nettype none | 02:45 |
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| whitequark | mithro: (joke answer) pip install nmigen | 05:57 |
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| ZirconiumX | So, I compared ABC9 sequential synthesis for synth_intel_alm. It seems to help at least a little bit area-wise | 12:51 |
| ZirconiumX | There's a very slight dip in Fmax, but I'm willing consider it noise | 12:52 |
| ZirconiumX | https://gist.github.com/ZirconiumX/a9b2c4bc7f5be27962415d698e5495cf | 12:52 |
| tpb | Title: dff.txt ยท GitHub (at gist.github.com) | 12:52 |
| qu1j0t3 | 31 | 12:52 |
| ZirconiumX | cc whitequark and mwk | 12:52 |
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| tnt | ZirconiumX: I tried -dff on a design of mine : https://pastebin.com/LeLxEvix | 17:47 |
| tpb | Title: Min Avg Max abc-nomince clk_30m72: 23.460000 26.6 - Pastebin.com (at pastebin.com) | 17:47 |
| ZirconiumX | tnt: it's ABC9 *and* dff which is the new bit | 17:47 |
| tnt | (comparing abc / abc9 / abc9+dff each with dffe_min_ce and without. 64 PNR runs) | 17:48 |
| tnt | I know. | 17:48 |
| ZirconiumX | It wasn't clear from your pastebin, sorry | 17:48 |
| ZirconiumX | Is clk_30m72 meant to be 30.72 MHz? | 17:49 |
| tnt | yup | 17:49 |
| tnt | It did meet it at some point in the past :/ | 17:50 |
| ZirconiumX | So dff seems to help a reasonable amount there actually | 17:50 |
| ZirconiumX | Not so much for the 30.72 MHz path, but | 17:51 |
| tnt | huh ? Where do you see thast it helps ? | 17:51 |
| ZirconiumX | I'm looking mostly at worst-case numbers here. | 17:52 |
| ZirconiumX | Okay, maybe I'm struggling to parse the numbers here | 17:53 |
| ZirconiumX | This probably wants like a candle chart or something | 17:53 |
| ZirconiumX | I'm presuming this is iCE40 | 17:54 |
| ZirconiumX | Hmm... | 17:55 |
| tnt | UP5k yes. | 17:55 |
| tnt | args to yosys were -abc9 -device u -dff | 17:56 |
| tnt | something to compare the histograms would be useful but ... I don't have anything like that. | 17:56 |
| tnt | it might just be that the critical path really can't be helped much. | 17:57 |
| ZirconiumX | tnt: matplotlib | 17:57 |
| tnt | I meant, I have nothing already written that takes a bunch of .log from nextpnr and extracts / aggregates / display the interesting bits :p | 17:58 |
| ZirconiumX | Y'know, I wrote a script to statistically test two builds of *something* | 17:59 |
| ZirconiumX | Maybe I should put it to work | 17:59 |
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| rlee287 | Is there an explanation in the Yosys manual or elsewhere as to why RTLIL::Process objects cannot always be mapped to Verilog always blocks? | 18:06 |
| rlee287 | (Asking because I would like to check if similar limitations exist for VHDL processes) | 18:06 |
| ZirconiumX | rlee287: simply because they're not implemented | 18:07 |
| ZirconiumX | VHDL isn't even *relevant*, because Yosys doesn't speak VHDL | 18:07 |
| rlee287 | I'm writing a VHDL backend right now to put it into the GHDL Yosys plugin | 18:07 |
| rlee287 | This would inform my decision on how to handle RTLIL Processes in this backend | 18:07 |
| ZirconiumX | whitequark is probably a good person to ask | 18:07 |
| whitequark | rlee287: there is no such clear explanation unfortunately | 18:08 |
| whitequark | and I don't fully understand it myself, but I did investigate this for a small amount of time | 18:09 |
| whitequark | (ideally there wouldn't be such a warning, it would just be a hard error on specifically the kinds of processes that aren't valid) | 18:09 |
| whitequark | ZirconiumX: I think that's not a matter of implementation | 18:09 |
| whitequark | or well, not just that | 18:09 |
| rlee287 | Thanks (which means I will need to run experiments on my own end to see what happens) | 18:10 |
| whitequark | rlee287: so the `case` part of a process can always be mapped to Verilog because it's just a combinatorial always @* block | 18:10 |
| whitequark | you could even say always_comb, since it is illegal to have a latch in that part | 18:10 |
| whitequark | the `sync` part is more troublesome though because there are some patterns that I think are not expressible in Verilog | 18:11 |
| whitequark | it's... somewhat hard to say which precisely, because, strictly speaking, Verilog contradicts itself here | 18:11 |
| whitequark | 1164.1 requires you to use some constructs that would always result in a significant sim/synth mismatch | 18:11 |
| whitequark | so the answer to "is this transformation of an RTLIL::Process to Verilog valid?" is "who the hell knows" | 18:12 |
| rlee287 | 1164 is referring to the IEEE standard 1164 about "STD_LOGIC" (or the Verilog equivalent of it)? | 18:12 |
| whitequark | err | 18:12 |
| ZirconiumX | 1364 | 18:12 |
| whitequark | 1364.1, sorry, I typoed | 18:12 |
| rlee287 | OK | 18:13 |
| whitequark | 1364 describes Verilog (the simulation language), 1364.1 describes Verilog (the synthesis language) | 18:13 |
| whitequark | it was supposed to be a synthesis subset but it clearly isn't | 18:13 |
| awygle | does vhdl have a synthesis subset? | 18:31 |
| awygle | (also hi rlee) | 18:31 |
| rlee287 | Hi awygle | 18:34 |
| rlee287 | Not that I am aware of (I vaguely recall people in the Discord saying that VHDL was slightly more problematic(?) because it did not define a synthesis subset) | 18:34 |
| rlee287 | It seems though based on whitequark's remakrs that Verilog's synthesis subset has problems as well | 18:35 |
| awygle | that is correct if not understated | 18:36 |
| awygle | and SV has no synthesis subset at all | 18:36 |
| awygle | (no formal one that is) | 18:36 |
| whitequark | ^ | 18:39 |
| whitequark | neither SV nor VHDL are strictly speaking suitable for synthesis as-is | 18:40 |
| whitequark | they're both event-driven simulation languages. at least VHDL has an actually nice and deterministic simulation model | 18:40 |
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