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| ashfaq1717 | hi all | 04:27 |
|---|---|---|
| ashfaq1717 | I'm doing synthesization of Single Cycle RISCV Processor, when I synthesize top module of processor, I have a problem when run 'hierarchy -check' command, I get error this ALU, (ALU instantiation) is not part of the design. This error comes for all instantiations....Can somebody help me, why is it? | 04:32 |
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| ZipCPU | ashfaq1717: You need to read the verilog files for the rest of the design into Yosys. Typically, this is done via the "read_verilog" command, although I kind of like using "read -sv filename.v" myself. | 12:06 |
| ZirconiumX | Or pass them on the command line | 12:11 |
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| Forty-Bot | does verilator support +: in declarations? | 22:41 |
| Forty-Bot | e.g. something like "wire [0 +: 32] foo;" | 22:41 |
| Forty-Bot | I can use that syntax fine in yosys, and it seems to be allowed by the standard | 22:41 |
| Forty-Bot | but verilator gives a syntax error | 22:41 |
| Forty-Bot | am I missing some kind of compiler option? | 22:42 |
| whitequark | Forty-Bot: doesn't seem to be allowed per 1364 | 22:43 |
| Forty-Bot | ok, so I'm looking at 1364-2005 on page 504-505 and +: is defined as a valid constant_range_expression | 22:45 |
| whitequark | yes but a type declaration uses a `range`, not a `constant_range_expression` | 22:46 |
| Forty-Bot | then on page 506, a net_lvalue is defined as an identifier plus a constant_range_expression | 22:46 |
| Forty-Bot | is that just for assign? | 22:46 |
| whitequark | yes | 22:46 |
| whitequark | that's what an lvalue is: a value on lhs of assignment | 22:47 |
| Forty-Bot | ah, ok thanks | 22:47 |
| Forty-Bot | it's kinda strange that it's not allowed for declarations | 22:47 |
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| whitequark | what would that mean for declarations? | 23:00 |
| Forty-Bot | the same thing it means for l-values? | 23:06 |
| whitequark | oh, i see what you mean | 23:06 |
| whitequark | or rather why you want it | 23:07 |
| whitequark | that seems inconsistent syntactically | 23:07 |
| Forty-Bot | yes | 23:07 |
| whitequark | no, i mean, being able to use :+ seems | 23:07 |
| whitequark | from my point of view, but i also see yours | 23:07 |
| Forty-Bot | the real issue, is if you want to have "one true range-specifier" it has to be : | 23:08 |
| Forty-Bot | and : can be rather unweildy for certain expressions | 23:08 |
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| whitequark | ahhh | 23:09 |
| whitequark | ok, that makes sense | 23:09 |
| Forty-Bot | another example, say I have two variables which are WIDTH wide, and I want to add them | 23:10 |
| Forty-Bot | the result will be WIDTH + 1 wide, but specifying it like "wire [WIDTH:0] sum"... almost looks like a typo | 23:10 |
| Forty-Bot | whereas "wire [0 +: WIDTH + 1] sum" is obviously supposed to be WIDTH + 1 wide | 23:11 |
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