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| tnt | mwk: the up5k spram can't even be init to zero, content is random on start. | 04:57 |
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| sensille | can i tell yosys to complain about uninitialized registers? | 08:42 |
| sensille | or to assume them as zero? | 08:43 |
| tnt | if you care about its initial value you should have a reset on it. | 09:20 |
| sensille | in case of fpgas, isn't the initial value part of the bitstream? or at least fixed as 0? | 09:22 |
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| daveshah | Which FPGA? | 09:22 |
| sensille | ecp5 in my case | 09:22 |
| daveshah | then the initial value is the same as the reset value | 09:22 |
| daveshah | defaulting to 0 if there is no reset and no init | 09:22 |
| daveshah | note that there are a few places where a sync reset may be inferred even if there isn't an obvious reset in the design | 09:22 |
| sensille | i just want yosys to warn me in case i forget an initial value | 09:23 |
| daveshah | (e.g. q <= sel ? 1'b1 : d) would infer a sync set and therefore q would default to one-initialised | 09:23 |
| tnt | sensille: sure but for instance if you're using a PLL you should hold all your logic in reset until it locks because until then the clock can do whatever ... | 09:23 |
| daveshah | I don't think there's a way to do that | 09:23 |
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| sensille | unfortunately verilator doesn't handle uninitialzed values well, either | 09:24 |
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| keith-man | This might sound weird, but fun I was think of trying to use yosys to synthesize with discrete gates. I can see that it can accept liberty files, but when searching for how to write one it seems like they can be quite complicated. When I all I wanted to do was mainly have delay, rise and fall times, and pin capacitance area. Just to try something | 11:38 |
| keith-man | out quickly. | 11:38 |
| keith-man | Also when looking I see that abc can use a genlib file which seems simpler. | 11:38 |
| keith-man | would perhaphs better to generate a bliff from a Verilog file and then use abc directly? | 11:38 |
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| ZirconiumX | Ugh, they're gone | 11:57 |
| mwk | well, it's a publicly logged channel, you can just answer into the aether | 12:01 |
| Sarayan | beware, the abyss^Waether may answer back | 12:02 |
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| ZirconiumX | It's entirely possible to use Yosys to synthesize to discrete gates; I even got it to target 74xx ICs: https://github.com/ZirconiumX/74xx-liberty | 12:40 |
| tpb | Title: GitHub - ZirconiumX/74xx-liberty (at github.com) | 12:40 |
| ZirconiumX | The Liberty format is a bit tricky to use, but I'm pretty sure ABC doesn't understand any of the timing information that comes with it | 12:41 |
| daveshah | It should do... | 12:41 |
| daveshah | whether it actually does is another question | 12:41 |
| ZirconiumX | Describing timing information in Liberty format is...tricky | 12:41 |
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| ZirconiumX | keith-man: check the channel logs, I replied to you there | 12:45 |
| keith-man | I just was looking there. Saw the mention of 7400 series logic, that's similar to what I want to do. | 12:46 |
| keith-man | zirconiumX: wait ABC may not use the timing info in a liberty file? | 12:48 |
| ZirconiumX | "may"; it's difficult to know exactly for sure because ABC is kinda opaque | 12:49 |
| keith-man | what about for a genlib? Looks like something ABC can also use. | 12:50 |
| ZirconiumX | I can't help you there, unfortunately | 12:54 |
| keith-man | so looking at the lib file you wrote here is there capacitance was only specified on some cell's pins? Like the hex-invert but not the others? https://github.com/ZirconiumX/74xx-liberty/blob/master/74ac.lib | 12:57 |
| tpb | Title: 74xx-liberty/74ac.lib at master · ZirconiumX/74xx-liberty · GitHub (at github.com) | 12:57 |
| ZirconiumX | Correct, but it seems to have made little difference without timing information | 12:57 |
| ZirconiumX | I struggled to work out how to specify it, which is why it's commented out | 12:58 |
| keith-man | ZirconiumX: Fair enough looking at the liberty handbook I found, the format looks like can do it a lot, but the little bit I have found on genlib seems simpler at least to me. https://people.eecs.berkeley.edu/~alanmi/publications/other/SIS_paper_genlib.pdf | 13:05 |
| keith-man | I guess I'll just have to experiment once I am less sleepy. It's really early in the morning for me I should probably sleep. | 13:18 |
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| ross_s | Has anyone seen the error 'Failed to find a route for arc 125 of net $PACKER_GND_NET'? Attempting to synthesize a 36 bit mult on the ECP5, using a clarity designer generated file consisting of 4 direct mult18x18ds and two alu54bs | 18:08 |
| daveshah | The ALU54B isn't fully working yet | 18:09 |
| ross_s | is there anything a layperson can do to help out? | 18:09 |
| daveshah | In particular there is nothing to correctly constrain the ALU54B and MULT18X18D together | 18:10 |
| daveshah | The most useful thing to do is put the design somewhere so I can have a look | 18:10 |
| daveshah | Particularly if it is something that can easily be tested on hardware | 18:10 |
| daveshah | Also, if you would be able to build it in Diamond and take a screenshot of the placement in physical view and provide the Diamond bitstream, that would also make it much quicker for me to finish | 18:11 |
| ross_s | ought to be - I've been trying to work out how the pipeline stuff works (since default inferred 18x18 is a bit slow), so I just have a test case that exposes a shift interface to the mult | 18:11 |
| ross_s | ok; I'll get the test code up somewhere and work on the diamond stuff | 18:12 |
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| ross_s | alright, here's a repo with some test code that should work: https://github.com/rschlaikjer/ecp-alu-sample | 18:40 |
| tpb | Title: GitHub - rschlaikjer/ecp-alu-sample (at github.com) | 18:40 |
| ross_s | running make will generate the error I mentioned above | 18:41 |
| ross_s | and I have now just pushed a commit that adds a diamond-generated bitstream to that repo | 18:43 |
| daveshah | Thanks! | 18:50 |
| ross_s | oops just remembered you wanted a screenshot of the physical view as well | 18:50 |
| ross_s | that's in there as well now | 18:50 |
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| ross_s | Related to previous discussion, does anyone know of a better DSP documentation resource than TN1267? | 23:06 |
| ross_s | Through trial and error I've verified that .REG_OUTPUT_CLK("CLK0") adds once cycle latency, and similarly setting REG_INPUT{A,B}_{CLK,CE,RST} adds a second one, but .REG_PIPELINE_{RST,CE,CLK} doesn't appear to do anything? I can't find example timing diagrams anywhere. | 23:06 |
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| ross_s | Do the pipeline registers only take effect if the mult is chained into an alu perhaps? | 23:06 |
| ross_s | It also looks like the in/out register config on the mult block isn't accounted for in the nextpnr timing, I can make a PR for that along the same lines as https://github.com/YosysHQ/nextpnr/pull/423 if I'm correct in thinking that setting both .REG_INPUT{A,B}_CLK to a non-"NONE" value enables the in registers | 23:06 |
| tpb | Title: Add support for REGMODE to DP16KD by rschlaikjer · Pull Request #423 · YosysHQ/nextpnr · GitHub (at github.com) | 23:06 |
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