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| strubi | Hi there, sorry for the first newbie question, possibly: I'm playing with RAM inference, in particular, I'd wanted to get some true dual port RAM working. Is it sufficient to modify what's in share/<arch and techlibs/<arch>? | 17:29 |
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| strubi | (arch is ECP5, in this case) | 17:29 |
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| daveshah | No, the Yosys BRAM passes don't support it at all | 17:31 |
| daveshah | There are a few possible ways you could hack it but truth be told the BRAM inference code is enough of a mess as it stands | 17:32 |
| strubi | So, it would involve touching `./passes/memory/memory_bram.cc` as well? | 17:33 |
| daveshah | Yes | 17:34 |
| daveshah | Or burning it and starting again, which would probably be the more tempting option | 17:34 |
| strubi | Uh oh. Well, I assume there's a test bench.. | 17:34 |
| daveshah | Yes, although plenty of subtle untested bugs have cropped up in bram code in the past | 17:35 |
| strubi | I think I've run into some. But really hard to tell, as I'm playing with the GHDL side, mostly | 17:35 |
| strubi | But now mimicking things in Verilog, there's some weirdness as well | 17:36 |
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| strubi | daveshah, what I can see so far in the synth .dot output ('show') is that different clocks (like a_clk, b_clk) seem to not correctly map to the $mem entity in the first place. | 19:14 |
| strubi | tried both verilog and VHDL | 19:15 |
| strubi | I | 19:18 |
| strubi | Not sure, but it looks like it's happening during the memory_collect pass | 19:19 |
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| daveshah | strubi: can you give an example? | 19:30 |
| strubi | Let me see where I can drop this | 19:32 |
| strubi | ; | 19:35 |
| strubi | https://gist.github.com/hackfin/1201612defcea0aa6cbfa22f88113c9c | 19:35 |
| tpb | Title: Example TDP 2R1W · GitHub (at gist.github.com) | 19:35 |
| daveshah | strubi: it can't merge the clock into a_read because it doesn't support that pattern of transparent port | 19:40 |
| daveshah | see https://github.com/YosysHQ/yosys/issues/1087 | 19:40 |
| tpb | Title: Memory inference fails for read-after-write · Issue #1087 · YosysHQ/yosys · GitHub (at github.com) | 19:40 |
| strubi | Ah, ok. So it's known then. | 19:41 |
| daveshah | Indeed | 19:42 |
| strubi | Verilog parsing seems right though. So in pre.dot it's split up in $memrd and $memwr ports. GHDL doesn't do that and directly creates a $mem, obviously. | 19:43 |
| daveshah | Yes, the problem is in memory_dff | 19:43 |
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| strubi | Allright, now when working around the memory_dff issue (using the proper template for a read-after-write) the clocks map right. | 19:54 |
| strubi | Thanks for the hint! This helps to divide-et-impera :-) | 19:58 |
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