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| sensille | in yosys i use this: { UNIT_SYSTEM, ARGS_BITS'd0, 1'b0, 1'b1 }, ARG_BITS is a localparam, and yosys does not complain | 12:27 |
|---|---|---|
| sensille | but verilator isn't happy with it | 12:27 |
| sensille | what would be the verilog way to specify the length of the constant? | 12:28 |
| ZirconiumX | {ARG_BITS{1'b0}} | 12:30 |
| sensille | that would be a repeat count, right? | 12:31 |
| ZirconiumX | Yeah | 12:31 |
| sensille | let's say i have ARG_BITS'd25 | 12:31 |
| sensille | with ARG_BITS=6 | 12:31 |
| ZirconiumX | Oh dear, this begins to get into the murky parts of the Verilog LRM | 12:32 |
| sensille | there seem to be a cast, but yosys does not accept it | 12:32 |
| sensille | that is an array assignment. i could split it into multiple arrays and let the assign do the truncate | 12:34 |
| sensille | and hope the result is the same | 12:34 |
| ZirconiumX | whitequark: from above, how can you cast a number to a localparam-specified width? | 12:36 |
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| ZirconiumX | (assuming I'm understanding you correctly, sensille) | 12:36 |
| sensille | you do | 12:37 |
| ZirconiumX | I'll have to investigate what Yosys does | 12:38 |
| ZirconiumX | Since I think I know what the cell would be | 12:38 |
| sensille | or i make everthing just 'wide enough' and let synthesis throw away the unused bits | 12:38 |
| sensille | but i'd like to avoid warnings where possible | 12:38 |
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| sensille | (i'm still in the early learning stages of verilog) | 12:39 |
| ZirconiumX | Hmm | 12:41 |
| ZirconiumX | Does verilator accept `ARG_BITS'('d25)`? | 12:42 |
| sensille | yes, but yosys doesn't | 12:44 |
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| natanelho | hello. I am new to fpga design in general but I know vhdl. I have a 7-series zynq z7020 board, how do I start with programming for it? | 12:58 |
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| ZirconiumX | natanelho: Yosys doesn't directly support VHDL at present | 13:27 |
| ZirconiumX | But you can try ghdlsynth as a front-end | 13:28 |
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| Cerpin | Are there still any plans to implement this? https://github.com/YosysHQ/yosys/issues/1134 | 14:52 |
| tpb | Title: Synthesis of asymmetric block RAMs · Issue #1134 · YosysHQ/yosys · GitHub (at github.com) | 14:52 |
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| mwk | Cerpin: definitely | 15:10 |
| mwk | I'll look into it in a month or two (once I'm done with my current tasks) | 15:10 |
| Cerpin | Awesome! | 15:13 |
| mwk | this is a hard issue unfortunetely, as it ties into a long-overdue full redesign of yosys blockram inference | 15:14 |
| mwk | but, this is finally on the roadmap | 15:15 |
| Cerpin | Ahh, right | 15:15 |
| Sarayan | what is an integrated logic analyzer actually? I mean at a concrete level, not a high-level idea? | 15:16 |
| mwk | Sarayan: in its simplest variant, a big RAM where you write values of all your monitored signals every cycle starting from your trigger cycle, until you run out of it | 15:17 |
| mwk | with a secondary port connected to some interface that allows you to read it out at your leisure (eg. JTAG) | 15:17 |
| Sarayan | so that's something hardware only, or it has a software sim side too? | 15:18 |
| mwk | well there's not much reason to do such a thing in sim | 15:19 |
| mwk | given that you already see all your signals in simulation anyway | 15:19 |
| Sarayan | I see | 15:20 |
| mwk | it's something that you use when your design works in simulation, but craps itself on real hardware, and you have no idea why | 15:20 |
| Sarayan | having that in a generated fpga firmware is very heisenberg though, right? I probably massively changes the behaviour in the first place? | 15:21 |
| Sarayan | It | 15:21 |
| mwk | it could | 15:21 |
| Sarayan | especially timings | 15:21 |
| mwk | but FPGAs are mostly deterministic | 15:21 |
| Sarayan | which, from what I understand, is the #1 case of "it's not running in hardware" | 15:21 |
| mwk | unless CDCs are involved | 15:22 |
| Sarayan | ah yeah | 15:22 |
| mwk | or unless you don't pass timing, but that is an obvious issue you should fix anyway | 15:22 |
| mwk | but... there's a different problem | 15:22 |
| mwk | inserting an ILA could very well cause you to no longer pass timing | 15:22 |
| mwk | so yeah, tricky | 15:23 |
| Cerpin | This is a fun discussion considering I work with someone who uses Xilinx's ILA as a debugging tool of first resort :\ | 15:23 |
| mwk | also — another case when you need an ILA is when you're interfacing to some other hardware which you cannot easily simulate | 15:23 |
| mwk | like, no amount of simulation will help you if it turns out that this external chip you talk to behaves differently than you thought | 15:24 |
| Sarayan | yeah indeed | 15:24 |
| mwk | ... yes, ILAs can be used as a first-line debugging tool | 15:24 |
| mwk | which is a supremely bad idea | 15:24 |
| mwk | but that's never stopped anyone, now has it | 15:25 |
| Sarayan | so I guess the question I should ask myself is how to make (nmigen+)yosys a nicer environment for debugging before hitting hardware | 15:25 |
| Sarayan | because I suspect it could be much better | 15:25 |
| Sarayan | but that requires smart UI work | 15:26 |
| Sarayan | dunno if I'm smart enough :-) | 15:27 |
| Cerpin | Supremely bad indeed | 15:35 |
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| ZirconiumX | Why does nextpnr output solely to stderr? | 16:18 |
| emily | all it outputs is diagnostics, right? | 16:18 |
| ZirconiumX | If you consider "the program output" to be diagnostics, sure | 16:18 |
| emily | stdout would be for if it was, like, dumping a bitstream on stdout | 16:20 |
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