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| ckqee | Hi | 14:48 |
|---|---|---|
| ZirconiumX | Hello | 14:51 |
| ckqee | :-) is this the right place to ask questions about yosys and nextpnr? | 14:52 |
| ckqee | I see an issue when installing nextpnr$ cmake -DARCH=ice40 .CMake Warning at /usr/local/share/cmake-3.16/Modules/FindBoost.cmake:2020 (message): No header defined for python-py369; skipping header check (note: header-only libraries have no designated component)Call Stack (most recent call first): CMakeLists.txt:157 (find_package) | 14:55 |
| daveshah | That warning is a spurious cmake issue | 14:55 |
| ckqee | i see the following though | 14:59 |
| ckqee | find /usr/lib/x86_64-linux-gnu/ -name libboost_python*so/usr/lib/x86_64-linux-gnu/libboost_python3.so/usr/lib/x86_64-linux-gnu/libboost_python-py36.so/usr/lib/x86_64-linux-gnu/libboost_python-py27.so/usr/lib/x86_64-linux-gnu/libboost_python3-py36.so/usr/lib/x86_64-linux-gnu/libboost_python.so | 14:59 |
| ckqee | i checked this https://github.com/YosysHQ/nextpnr/issues/87 but i cannot get past it | 15:00 |
| tpb | Title: Error on install · Issue #87 · YosysHQ/nextpnr · GitHub (at github.com) | 15:00 |
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| ckqee | i am using Ubuntu 18.04.4 LTSI don't know how to over come the cmake issue | 15:03 |
| ckqee | according to the issue#87 - i cannot find "Did you run ./download-latest-db.sh inside the prjtrellis folder" from 2018 - looks like it does not exist any more | 15:05 |
| daveshah | Is cmake actually failing? What happens if you run make -j7 | 15:05 |
| daveshah | The download-latest-db is no longer needed | 15:06 |
| ckqee | i get | 15:06 |
| ckqee | make -j`nproc`make: *** No targets specified and no makefile found. Stop. | 15:06 |
| daveshah | What is the full cmake output? You've only posted a warning not an error | 15:06 |
| ckqee | Makefile creation has not completed to what i understand it to be | 15:06 |
| ckqee | user1@machine:~/github/YosysHQ$ git clone https://github.com/YosysHQ/nextpnrCloning into 'nextpnr'...remote: Enumerating objects: 249, done.remote: Counting objects: 100% (249/249), done.remote: Compressing objects: 100% (133/133), done.remote: Total 15743 (delta 154), reused 191 (delta 116), pack-reused 15494Receiving objects: 100% (15743/15743), | 15:08 |
| ckqee | 6.28 MiB | 5.39 MiB/s, done.Resolving deltas: 100% (11514/11514), done.user1@machine:~/github/YosysHQ$ cd nextpnr/user1@machine:~/github/YosysHQ/nextpnr$ cmake -DARCH=ice40 .-- The C compiler identification is GNU 7.4.0-- The CXX compiler identification is GNU 7.4.0-- Check for working C compiler: /usr/bin/cc-- Check for working C compiler: | 15:08 |
| ckqee | /usr/bin/cc -- works-- Detecting C compiler ABI info-- Detecting C compiler ABI info - done-- Detecting C compile features-- Detecting C compile features - done-- Check for working CXX compiler: /usr/bin/c++-- Check for working CXX compiler: /usr/bin/c++ -- works-- Detecting CXX compiler ABI info-- Detecting CXX compiler ABI info - done-- Detecting | 15:08 |
| ckqee | CXX compile features-- Detecting CXX compile features - done-- Found PythonInterp: /usr/bin/python3.5 (found suitable version "3.5.2", minimum required is "3.5") -- Found PythonLibs: /usr/lib/x86_64-linux-gnu/libpython3.6m.so (found suitable version "3.6.9", minimum required is "3.5") -- Looking for pthread.h-- Looking for pthread.h - found-- | 15:08 |
| ckqee | Performing Test CMAKE_HAVE_LIBC_PTHREAD-- Performing Test CMAKE_HAVE_LIBC_PTHREAD - Failed-- Looking for pthread_create in pthreads-- Looking for pthread_create in pthreads - not found-- Looking for pthread_create in pthread-- Looking for pthread_create in pthread - found-- Found Threads: TRUE -- Found Boost: /usr/include (found version "1.65.1") | 15:08 |
| ckqee | found components: filesystem thread program_options iostreams system chrono date_time atomic regex -- Found OpenGL: /usr/lib/x86_64-linux-gnu/libOpenGL.so CMake Warning at /usr/local/share/cmake-3.16/Modules/FindBoost.cmake:2020 (message): No header defined for python-py369; skipping header check (note: header-only libraries have no designated | 15:08 |
| ckqee | component)Call Stack (most recent call first): CMakeLists.txt:157 (find_package)CMake Warning at /usr/local/share/cmake-3.16/Modules/FindBoost.cmake:2020 (message): No header defined for python-py36; skipping header check (note: header-only libraries have no designated component)Call Stack (most recent call first): CMakeLists.txt:164 | 15:08 |
| ckqee | (find_package)CMake Error at CMakeLists.txt:199 (find_package): Could not find a package configuration file provided by "Eigen3" with any of the following names: Eigen3Config.cmake eigen3-config.cmake Add the installation prefix of "Eigen3" to CMAKE_PREFIX_PATH or set "Eigen3_DIR" to a directory containing one of the above files. If | 15:08 |
| ckqee | "Eigen3" provides a separate development package or SDK, be sure it has been installed.-- Configuring incomplete, errors occurred!See also "/home/user1/github/YosysHQ/nextpnr/CMakeFiles/CMakeOutput.log".See also "/home/user1/github/YosysHQ/nextpnr/CMakeFiles/CMakeError.log".user1@machine:~/github/YosysHQ/nextpnr$ | 15:08 |
| ckqee | @daveshah - thank you for helpng me :-) | 15:08 |
| daveshah | You need to install eigen3 | 15:08 |
| daveshah | and the development package for it, if applicable | 15:09 |
| ckqee | Thank you ! that worked did | 15:10 |
| ckqee | sudo apt-get install libeigen3-dev | 15:10 |
| ckqee | i spoke (typed) too soon - | 15:12 |
| ckqee | i now see the following | 15:12 |
| ckqee | [ 13%] Building CXX object generated/3rdparty/QtPropertyBrowser/src/CMakeFiles/QtPropertyBrowser.dir/qttreepropertybrowser.cpp.o[ 15%] Building CXX object generated/3rdparty/QtPropertyBrowser/src/CMakeFiles/QtPropertyBrowser.dir/qtvariantproperty.cpp.o[ 16%] Building CXX object | 15:12 |
| ckqee | generated/3rdparty/QtPropertyBrowser/src/CMakeFiles/QtPropertyBrowser.dir/qrc_qtpropertybrowser.cpp.o[ 17%] Linking CXX static library libQtPropertyBrowser.a[ 17%] Built target QtPropertyBrowserMakefile:129: recipe for target 'all' failedmake: *** [all] Error 2 | 15:12 |
| ckqee | i'm going to start again and follow the following instructions | 15:14 |
| ckqee | http://www.clifford.at/icestorm/ | 15:14 |
| tpb | Title: Project IceStorm (at www.clifford.at) | 15:14 |
| ckqee | thank you for helping too @tpb | 15:14 |
| ckqee | :-) | 15:14 |
| ckqee | i noticed some people write make -j`nproc` and some write make -j$(nproc) | 15:16 |
| ckqee | i was toying with the idea of using Vivado to view the schematic netlist out of yosys. - i have to create a Verilog simulation cell library that defines all the cells in a particular liberty.lib file | 15:19 |
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| emily | ... is the old and mostly obsolete shell syntax | 15:20 |
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| ZirconiumX | emily: I think half your message got cut off | 15:22 |
| ckqee | hmm -i am showing my age? :-| | 15:22 |
| emily | ZirconiumX: are you sure? | 15:22 |
| emily | I was responding to ckqee | 15:22 |
| ZirconiumX | "<emily> ... is the old and mostly obsolete shell syntax" | 15:22 |
| ckqee | emily - which unix/*nix shell do you use? | 15:22 |
| ZirconiumX | https://freenode.irclog.whitequark.org/yosys/2020-02-14#26375261; | 15:23 |
| tpb | Title: #yosys on 2020-02-14 — irc logs at whitequark.org (at freenode.irclog.whitequark.org) | 15:23 |
| ZirconiumX | emily uses NixOS | 15:23 |
| emily | oh huh | 15:24 |
| emily | there were meant to be backticks around the ... | 15:24 |
| emily | I guess weechat-matrix messes it up :/ | 15:24 |
| ckqee | i did not know about NixOS! | 15:25 |
| ckqee | learning something new :-) | 15:25 |
| emily | I use fish as my shell. it's not Bourne sh/bash/zsh/... compatible though. | 15:25 |
| ZirconiumX | You should always use $(...), especially since it's POSIX | 15:25 |
| ZirconiumX | And nestable | 15:25 |
| ckqee | i now understand | 15:25 |
| ckqee | one question about verilog if i may | 15:26 |
| ZirconiumX | emily: I really like fish and really hate fish at the same time >.> | 15:26 |
| emily | I've spent the past few minutes trying to dig up a citation for when exactly $(...) originates | 15:26 |
| ckqee | when you have a reg myregA = 0; | 15:26 |
| emily | since I'm curious now | 15:26 |
| ckqee | some asic tools complain right? | 15:26 |
| emily | ZirconiumX: what do you hate about it? most of the nits I had with it are fixed. I wish it supported subshells natively | 15:26 |
| ckqee | but FPGA tools seem to be ok with it? | 15:26 |
| ZirconiumX | That's not synthesisable for ASICs because ASIC flip-flops are not initialisable | 15:26 |
| emily | ZirconiumX: btw you can nest backticks, it's just horrible. | 15:26 |
| ZirconiumX | However, FPGA flip-flops are | 15:27 |
| emily | foo \bar \\\baz\\\\ | 15:27 |
| emily | ... | 15:27 |
| ckqee | what is the workaround to migrate the fpga code to asic? | 15:27 |
| emily | right, matrix. | 15:27 |
| emily | uh. hm. | 15:27 |
| emily | foo \bar \\\baz\\\\ | 15:27 |
| ckqee | Thank you ZirconiumX | 15:27 |
| emily | if that didn't send properly then i don't care. | 15:27 |
| ZirconiumX | ckqee: Have a reset input, and then `always @(posedge clk) begin if (reset) myregA <= 0; else begin ... end end` | 15:28 |
| ckqee | Now that makes sense with what I am reading up on. so that coding style is specific to asic | 15:28 |
| ZirconiumX | It's feasible to do it on FPGAs too | 15:29 |
| ZirconiumX | It's just that FPGAs generally have first-class support for it anyway | 15:29 |
| ckqee | so we should write ASIC RTL Verilog for FPGA which can then be easily migrated to ASIC tools without too much hassle? | 15:29 |
| ZirconiumX | Like most things: it depends | 15:30 |
| ckqee | wow i like the nextpnr gui - | 15:31 |
| ckqee | is there a logic schematic capability in it? | 15:31 |
| ZirconiumX | You definitely *can*, but code that is optimal for ASICs will likely result in majorly slow FPGA logic | 15:31 |
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| ckqee | thank you all - my local build of nextpnr works! | 15:31 |
| ckqee | :-) | 15:31 |
| ckqee | @ZirconiumX where can i read up on this please? | 15:32 |
| ZirconiumX | For example, an ASIC library might want to manually instantiate a memory tuned to the process, which an FPGA synthesis tool would have to build out of flops | 15:32 |
| ZirconiumX | I don't know, ckqee; it's knowledge I've accumulated in the...year-ish since I picked up FPGas | 15:33 |
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| ZirconiumX | daveshah: So, I've been running Fmax tests with --randomize-seed, but not setting an Fmax target. Is that a valid testing methodology, or will nextpnr produce worse results without a proper Fmax target? | 15:53 |
| ckqee | thank you for you help! ZirconiumX | 15:53 |
| ZirconiumX | You're welcome. | 15:54 |
| ckqee | Any ideas about getting a schematic view of the netlist? something like this https://tex.stackexchange.com/questions/231116/digital-circuits | 15:57 |
| tpb | Title: circuitikz - Digital circuits - TeX - LaTeX Stack Exchange (at tex.stackexchange.com) | 15:57 |
| daveshah | ZirconiumX: fine for the next few weeks, if/when I do timing driven rip up in router2 it might be a problem | 16:01 |
| ZirconiumX | daveshah: thanks, wanted to verify my testing methodology | 16:02 |
| daveshah | That approach won't also work with most vendor tools | 16:03 |
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| ZirconiumX | Unfortunately I don't have a copy of icecube and I'm not even sure if it's a supported backend for synth_ice40 | 16:04 |
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| meawoppl | hey all! | 18:59 |
| meawoppl | I am having a problem with yosys that I don't grock: | 19:00 |
| meawoppl | I am running the integration of several modules, any one of which seems to work well | 19:01 |
| meawoppl | but when I build them together I get this: | 19:01 |
| meawoppl | ERROR: Max frequency for clock 'myCameraSPIReader.rawByteStrobe_$glb_clk': 5.04 MHz (FAIL at 12.00 MHz) | 19:01 |
| meawoppl | I am not sure what to make of it | 19:02 |
| daveshah | Assuming the frequency of myCameraSPIReader.rawByteStrobe_$glb_clk is indeed 12MHz then you are doing too much in a clock cycle | 19:02 |
| meawoppl | yeah, there is some cascading logic in there about sampling, but the signal coming in should be.... like 100kHz tops | 19:03 |
| meawoppl | I am not sure how to hint the compiler that this is OK I guess | 19:03 |
| daveshah | add `set_frequency myCameraSPIReader.rawByteStrobe_$glb_clk 0.1` to the pcf file | 19:03 |
| daveshah | sorry, `set_frequency myCameraSPIReader.rawByteStrobe_ 0.1`, don't include the suffix | 19:04 |
| daveshah | * `set_frequency myCameraSPIReader.rawByteStrobe 0.1` | 19:04 |
| meawoppl | ahhh, fantastic! | 19:06 |
| meawoppl | where does the 12MHz figure come from? | 19:06 |
| daveshah | it's just a default based on the most common iCE40 designs | 19:06 |
| daveshah | you can change the default for all clocks using the `--freq` command line argument too | 19:06 |
| meawoppl | OIC | 19:07 |
| meawoppl | how does yosys decide which lines are clocks? | 19:07 |
| daveshah | it's nextpnr that decides | 19:08 |
| daveshah | anything connected to a clock sink port is a clock | 19:08 |
| daveshah | (that could be of an FF, BRAM, IO, etc) | 19:08 |
| meawoppl | ahhh, so anything that appears in a `posedge` list plus async assignment? | 19:09 |
| daveshah | async resets wouldn't count | 19:09 |
| daveshah | but the clock part of any `posedge` list would | 19:09 |
| meawoppl | makes sense! | 19:09 |
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| meawoppl | As a followup question, is there a way to hint it in code about these speeds? At present, whenever I add an instance of this module, I will run into this issue... | 19:17 |
| meawoppl | I have 1 here, but I will have 144 in the next version | 19:18 |
| daveshah | No, not currently. 144 different clocks sounds like a bad idea too | 19:18 |
| daveshah | There are 8 global clock signals. Once you exceed that clocks end up being routed using general routing which can cause horrible skew and hold time issues | 19:18 |
| meawoppl | Noted! I will have to rethink the sampling logics then. It should be fixed in that version, so I can do some simplification I suspect | 19:20 |
| meawoppl | fixed meaning constant | 19:20 |
| daveshah | Depending on where the signal comes from, using clock enables is often a better idea than new clock signals | 19:21 |
| meawoppl | OIC, like sharing the came clock buffer, then switching in and out the pieces using it? | 19:21 |
| daveshah | Yes. Usually this would be code like `always @(posedge clock) if (clock_enable) do_something;` | 19:22 |
| daveshah | Instead for example of dividing `clock` by 4, you could have `clock_enable` high one every 4 cycles | 19:23 |
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| peepsalot | ZirconiumX: i downloaded your intel branch. is there any specific simplified test case I should try on de10-nano to see what the exact errors you are dealing with? | 20:28 |
| ZirconiumX | Unfortunately nothing "simplified" | 20:29 |
| ZirconiumX | But if memory serves me correctly - christ it's been a while - try compiling something for Cyclone V and using -vqm, and then try that under Quartus | 20:29 |
| peepsalot | I've seen Quartus has some options for external "Design Entry/Synthesis" tools, and there is a Custom option, but looks like specifying a command to automatically run a custom option is not supported? | 20:41 |
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| peepsalot | Also, it has choices of Format: VQM, Verilog HDL, AHDL, and VHDL. I wonder if Verilog HDL would be any more compatible than VQM? | 20:44 |
| ZirconiumX | peepsalot: Verilog mode *is* more compatible, but it's also notably slower | 20:48 |
| ZirconiumX | In VQM mode Quartus just parses the file and turns it into the Quartus internal database format | 20:48 |
| peepsalot | for VQM can it use any "atom"/primitive? | 20:50 |
| peepsalot | i don't have any projects to try but mister stuff :/ , which i guess is a mix of incompatible VHDL etc. | 20:53 |
| ZirconiumX | Pretty much | 20:53 |
| peepsalot | ZirconiumX: do you think it would help to have some EBNF checker/validator that could be run on yosys output against the VQM spec from that QUIP doc? | 21:06 |
| ZirconiumX | Doesn't that essentially boil down to "the Verilog specification"? | 21:06 |
| peepsalot | idk, i mean, its a specific subset, right? | 21:07 |
| ZirconiumX | It's still a pretty general subset of the language | 21:07 |
| ZirconiumX | The restrictions don't mean too much in the grand scheme of things | 21:08 |
| Sarayan | Hey ZX, aren't you drowing in gigabytes of text? ;-) | 21:09 |
| ZirconiumX | Sarayan: I am, but I believe somebody else was writing a database extractor :P | 21:10 |
| Sarayan | huhuhu yes, I'm doing too many things at the same time | 21:10 |
| Sarayan | found interesting information in there or not yet? | 21:10 |
| ZirconiumX | Not yet, what with about a million different people wanting me for different things | 21:12 |
| ZirconiumX | peepsalot: perhaps you should join us in #prjmistral | 21:18 |
| Sarayan | ZX: We have similar lives :-) RIght now I'm re-ing a cpu from 3 program dumps and nothing else | 21:18 |
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