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| Duality | hi | 15:57 |
|---|---|---|
| Duality | is there any feasable way to revers a fpga bitstream image ? | 15:58 |
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| ZipCPU | Duality: Absolutely! | 16:05 |
| ZipCPU | Which tool you need and use, however, will depend upon which FPGA type you are working with | 16:06 |
| ZirconiumX | Or at least which FPGA family | 16:09 |
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| ZipCPU | As an example of what you might do with such a reversed capability, this project (https://github.com/ZipCPU/cputest-harness) takes an iCE40 image containing a RISC-V computer, adds a simulation for a QSPI flash and a serial port to it and allows you to interact with it | 16:36 |
| tpb | Title: GitHub - ZipCPU/cputest-harness: A simulation test harness, containing serial port, QSPI flash, and an output done I/O--just provide the CPU (at github.com) | 16:36 |
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| flokli | woah, very cool :-) | 18:24 |
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| az0re | Wait wait wait: You give it a complete iCE40 bitstream and it reconstructs the hardware it implements and adds a testbench around it, replacing actual FPGA I/Os with auto-generated testbench peripherals? | 18:45 |
| az0re | How does it recognize which FPGA I/Os are which peripherals? Do you need to have some hardcoded signal names in a .pcf or something? | 18:47 |
| az0re | ZipCPU^ | 18:47 |
| az0re | ZipCPU ^ * | 18:47 |
| flokli | https://imgflip.com/memetemplate/143723981/ | 18:54 |
| tpb | Title: hay ball Blank Template - Imgflip (at imgflip.com) | 18:54 |
| flokli | :-D | 18:54 |
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| ZipCPU | az0re: There's a PCF file in the project directory that can be adjusted to make sure the I/O's are properly mapped | 19:12 |
| ZipCPU | But, yes, I "give it a complete iCE40 bitstream and it reconstructs the hardware it implements and adds a testbench around it, replacing actual FPGA I/Os with auto-generated testbench peripherals." | 19:13 |
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| ZipCPU | wb2axip | 22:52 |
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