Monday, 2020-02-03

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mwkdaveshah: any opposition to https://github.com/YosysHQ/yosys/pull/1673 from your side, or should I just merge it?11:11
tpbTitle: Add opt_lut_ins pass. by mwkmwkmwk · Pull Request #1673 · YosysHQ/yosys · GitHub (at github.com)11:11
daveshahmwk: I haven't actually had a chance to test it yet. Does it ensure that mux structures for ECP5 are always still complete?11:12
daveshahnextpnr-ecp5 currently requires this11:13
mwkno, it can turn a LUT into a const11:14
mwkif it's not depending on *any* inputs11:14
daveshahAh, that will break then11:14
daveshahI can look at fixing the nextpnr side but can't guarantee that will be today11:15
mwkhmm11:16
daveshahAlthough it doesn't actually break11:16
mwkI can just disable this part for ecp5 and emit an all-0 or all-1 LUT4 instead11:17
daveshahIt seems to be doing that already?11:19
daveshahe.g.11:19
daveshahhttps://www.irccloud.com/pastebin/nxQzhSPS/11:20
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)11:20
mwkoh11:20
mwkit actually does that by an accident11:21
mwkbut yeah, it does work that way11:21
daveshahFine for me to be merged then11:21
mwk(because the "pad to 4 if ecp5" code is before the "check if 0 inputs" code)11:21
mwkI'll make this behavior more explicit11:23
daveshahThanks!11:23
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dkozelHi Folks. Just noticed that the sphinxcontrib-verilog-diagrams package is missing from pypi and cannot be installed (other than with git) via pip14:23
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