Friday, 2020-01-31

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FSM_DudeHey there! I'm running into trouble with synthesis when using Yosys. When I try to synthesise my design and afterwards use write_verilog. The output file does not only contain my module but also other modules such as: module AND2X1(A, B, Y);. This happens while my input design only has one module specified....14:22
FSM_DudeIt seems like yosys is making modules out of cell from the used cell library?14:22
FSM_DudeIs there anything I can do to prevent this?14:24
daveshahYes, write_verilog will write any black/whiteboxes too14:24
daveshahdelete a:blackbox might fix it before write_verilog14:25
ZipCPU|LaptopYosys is a synthesis tool.  That's what it is supposed  to do.  What cell library would you like to map to?14:25
FSM_DudeThanks Dave Ill look into that!14:28
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