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| parataxis | loading simlib.v is giving me an error: "/share/yosys/simlib.v:1485: ERROR: System task `$stop' outside initial block is unsupported." | 06:48 |
|---|---|---|
| parataxis | this is from a symbiyosis script, so it might be that simlib.v doesn't work in formal? | 06:48 |
| parataxis | oh, I should have used ice40/cells_sim.v | 06:53 |
| parataxis | is it normal for calling read_verilog +/ice40/cells_sim.v to use more than 8gb of memory | 07:07 |
| parataxis | it would have used more but that was as far as it got before being OOM killed | 07:08 |
| parataxis | read_verilog -lib +/ice40/cells_sim.v complains about `\SB_SPRAM256KA' (which I am using) being a "blackbox/whitebox module" | 07:13 |
| daveshah | I think you need to do read_verilog -DEQUIV +/ice40/cells_sim.v | 07:13 |
| daveshah | This is to do with how some memory is implemented | 07:14 |
| daveshah | Definitely not -lib, or you will only get blackboxes as the error says | 07:14 |
| parataxis | -DEQUIV gives me that same "blackbox/whitebox module" error | 07:14 |
| daveshah | Oh yeah, I see, the problem is that the way the SPRAM block is written is not one that Yosys supports - as it is intended for simulation | 07:17 |
| daveshah | Removing the EQUIV and commenting out this always block might fix it | 07:17 |
| daveshah | https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v#L1138 | 07:17 |
| tpb | Title: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at github.com) | 07:17 |
| parataxis | I'm trying to use yosys formal on a module that uses that ram block though | 07:18 |
| parataxis | I guess I'm not using the poweroff pin so it should be fine | 07:19 |
| parataxis | memory blows up again | 07:23 |
| parataxis | if it just needs more memory I can run it on a different machine but I susupect it isn't supposed to | 07:23 |
| daveshah | What solver are you using? | 07:27 |
| parataxis | smtbmc | 07:28 |
| parataxis | I don | 07:31 |
| parataxis | I don't think it gets to doing any searching though | 07:31 |
| parataxis | if I comment out the read -formal line the memory usage still blows up | 07:32 |
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| parataxis | reducing the size of the register in the sram stub fixes the memory blowup so that is the problem | 07:56 |
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| ZirconiumX | daveshah: What does "ABC: Timing manager is given but there is no GIA of boxes." mean? | 13:29 |
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| daveshah | ZirconiumX: my guess is that you haven't given it a functional model of the boxes | 13:30 |
| daveshah | If you don't have one, make sure that the white/black box flag in the box file is set to 0 | 13:30 |
| ZirconiumX | I do have a model, though :P | 13:31 |
| daveshah | it may still print that even if that is the case, I'm not sure as usually there are models for at least some boxes | 13:31 |
| daveshah | is it marked lib_whitebox ? | 13:31 |
| ZirconiumX | https://pastebin.com/pN2zWYrW | 13:31 |
| tpb | Title: [VeriLog] (* abc9_box_id = 1, lib_whitebox *) module MISTRAL_ALUT_ARITH(input A, B, C, D0 - Pastebin.com (at pastebin.com) | 13:31 |
| daveshah | Looks fine | 13:32 |
| somlo | ZirconiumX: ironically, bisect tells me commit 151f7533 is to blame (the commit introducing the test case that's bombing out for me :) ) | 13:32 |
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| ZirconiumX | This is printed by &mfs | 13:32 |
| dh73 | https://github.com/berkeley-abc/abc/pull/64/files | 13:32 |
| tpb | Title: Preserve pAigExtra when cleaning XAIG by eddiehung · Pull Request #64 · berkeley-abc/abc · GitHub (at github.com) | 13:32 |
| dh73 | try that one | 13:32 |
| ZirconiumX | It got merged into master, dh73 | 13:33 |
| ZirconiumX | https://github.com/berkeley-abc/abc/commit/144c5be8246800d5bd36dc3e177364063e8d2e40 | 13:33 |
| tpb | Title: Preserving additional AIG manager when dandling nodes are present. · berkeley-abc/abc@144c5be · GitHub (at github.com) | 13:33 |
| ZirconiumX | So it's in the version of ABC I have | 13:34 |
| FSM_Dude | So I have a verilog design which I read in to Yosys using: read_verilog input.v. This verilog design has some FSM in it, it is recognised and extracted by Yosys during synthesis. Now at the end of synthesis, I write the synthesised design to output.v. If I would then read_verilog output.v, should Yosys again recognise the FSM? | 13:35 |
| daveshah | Not if you've done significant synthesis | 13:36 |
| daveshah | FSM extraction is primarily intended to work with RTL, it also relies on the "RTL-style" cells like $mux rather than arbitrary gates | 13:36 |
| thasti | ls | 13:38 |
| FSM_Dude | Hmm okay, so after using techmap, dfflibmap and abc it's basically not possible anymore | 13:38 |
| daveshah | Indeed | 13:38 |
| FSM_Dude | Great thanks for the help! | 13:38 |
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| somlo | ZirconiumX: thanks again for helping me think through it yesterday. As it turns out, the problem had nothing to do with vendoring abc in yosys, and everything to do with Fedora's (relatively stringent) build-time CFLAGS, which I think uncovered some sort of bounds checking or array overflow bug: https://github.com/YosysHQ/yosys/issues/1663 | 17:31 |
| tpb | Title: tests/various/bug1531 fails when building with Fedora build flags · Issue #1663 · YosysHQ/yosys · GitHub (at github.com) | 17:31 |
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| ZirconiumX | somlo: can you send me /usr/lib/rpm/redhat/redhat-hardened-{cc1,ld} ? | 17:43 |
| sorear | my copy of those files are just forcing PIE and -z now, no array-related hardening | 17:46 |
| ZirconiumX | Right, okay | 17:47 |
| somlo | ZirconiumX: redhat-hardened-cc1: https://pastebin.com/ff6300aP ; redhat-hardened-ld: https://pastebin.com/ceksbQAq | 17:57 |
| tpb | Title: *cc1_options: + %{!r:%{!fpie:%{!fPIE:%{!fpic:%{!fPIC:%{!fno-pic:-fPIE}}}}}} - Pastebin.com (at pastebin.com) | 17:57 |
| somlo | daveshah: nextpnr also needs python 3.9 support: https://pastebin.com/q52CqYnU | 17:58 |
| tpb | Title: [Diff] diff --git a/CMakeLists.txt b/CMakeLists.txt index 8131d4a..92b5d18 100644 --- - Pastebin.com (at pastebin.com) | 17:58 |
| somlo | ZirconiumX: sorry, I just realized it's a bunch of rpm specfile gibberish... But, basically, what sorear said :) | 18:00 |
| ZirconiumX | somlo: So, I just followed the instructions you gave | 18:00 |
| ZirconiumX | Aaaand I have a completely *different* error | 18:00 |
| ZirconiumX | https://pastebin.com/4P95M1xa | 18:01 |
| tpb | Title: # +cd tests/realmath && bash run-test.sh "-S 314159265359" cd tests/share && ba - Pastebin.com (at pastebin.com) | 18:01 |
| ZirconiumX | Does this pass on your machine? | 18:01 |
| somlo | if tests/share are *before* tests/various in the top-level makefile, then yes :) | 18:02 |
| ZirconiumX | I mean, that's tests/realmath | 18:03 |
| somlo | `which rename` gives me "/usr/bin/rename", it's apparently a utility to "rename files"... | 18:03 |
| ZirconiumX | ...Huh. | 18:03 |
| somlo | either way, I'm fine all the way through tests/various, so anything listed before that in the "test" toplevel makefile target passes for me | 18:04 |
| somlo | ZirconiumX: interestingly enough, "tests/realmath" is commented out in the "master" version of the toplevel makefile, under the "tests" target | 18:05 |
| somlo | but it's before "various" | 18:05 |
| somlo | I'd be curious if you comment out all tests before "various", if it dies for you as well | 18:06 |
| somlo | incidentally, "/usr/bin/rename" on my (Fedora) box is part of the "util-linux-2.33.2-..." package | 18:07 |
| ZirconiumX | Mmm, so it's actually passing `rename` as a command to Yosys, (like I suspected) | 18:07 |
| ZirconiumX | (tests/realmath/generate.py:69) | 18:07 |
| somlo | which is why I assume it's commented out in the master branch afaict | 18:08 |
| ZirconiumX | ...It's commented out, why is it executing? | 18:09 |
| somlo | huh... | 18:09 |
| ZirconiumX | In other news I just learned that the testsuite that I went to the trouble of writing never actually gets called in CI. Go me. | 18:10 |
| ZirconiumX | At least I learned something from this :P | 18:10 |
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| somlo | I mean, *LOTS* of stuff flies by during `make test`, and it's all good until it hits "tests/various", and specifically bug1531.ys | 18:11 |
| somlo | that's with the vendored abc, or ABCEXTERNAL, doesn't matter as long as the Fedora CFLAGS are used | 18:11 |
| ZirconiumX | Sure enough. | 18:14 |
| ZirconiumX | /usr/include/c++/8/bits/stl_vector.h:932: std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::operator[](std::vector<_Tp, _Alloc>::size_type) [with _Tp = Yosys::RTLIL::State; _Alloc = std::allocator<Yosys::RTLIL::State>; std::vector<_Tp, _Alloc>::reference = Yosys::RTLIL::State&; std::vector<_Tp, _Alloc>::size_type = long unsigned int]: Assertion '__builtin_expect(__n < this->size(), true)' failed. | 18:14 |
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| ZirconiumX | somlo: https://github.com/YosysHQ/yosys/blob/master/frontends/ast/simplify.cc#L2607 | 18:20 |
| tpb | Title: yosys/simplify.cc at master · YosysHQ/yosys · GitHub (at github.com) | 18:20 |
| ZirconiumX | This is the crashing line | 18:20 |
| ZirconiumX | if (0) { case AST_BIT_AND: const_func = RTLIL::const_and; } | 18:29 |
| ZirconiumX | I'd forgotten about Claire's Device | 18:29 |
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| somlo | ouch, that's like the *opposite* of "minimal-WTF" :D | 18:32 |
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| somlo | "if it was hard to write, it should be hard to understand" :D | 18:34 |
| ZirconiumX | It's effectively a goto :P | 18:34 |
| Xiretza | two gotos, really, since it skips all the following `if (0)` and jumps straight to the end | 18:36 |
| somlo | also: https://www.google.com/search?q=kernighan%27s+law | 18:36 |
| tpb | Title: kernighan's law - Google Search (at www.google.com) | 18:36 |
| ZirconiumX | somlo: congrats, you found a bug | 18:45 |
| somlo | thanks, and sorry :D | 18:46 |
| ZirconiumX | Unfortunately I don't know the codebase well enough to diagnose much further :P | 18:46 |
| somlo | that's ok, at least I know I'm not crazy, that's not nothing! :) | 18:46 |
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