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| lukego | I'd like to meet all'yall open source hardware hackers at FOSDEM. Is there a particularly popular place to stay for this crowd i.e. hotel recommendation? | 09:58 |
|---|---|---|
| lukego | (I'm meanwhile setting up my dev env... learning to solder, going to make a power supply board, then going to try and put my ECP5 BGA and 10G ethernet PHY BGAs onto a first simple board of some kind...) | 10:03 |
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| corecode | when/where is fosdem? | 11:21 |
| lukego | Brussels, 1-2 december. https://fosdem.org/2020/ | 11:23 |
| tpb | Title: FOSDEM 2020 - Home (at fosdem.org) | 11:23 |
| lukego | I did catch fpgadave's talk about Project Trellis last year but I was mostly hanging out with the software networking crowd beyond that. | 11:24 |
| tnt | definitely not in december ... | 11:24 |
| lukego | er, feb :- | 11:24 |
| finnb | I went last year but felt it was a little too busy to actually attend a lot of the talks I wanted to see | 11:43 |
| tnt | you just can't change room ... | 11:45 |
| tnt | pick one, go in the morning, leave in the evening. | 11:45 |
| finnb | I think if you're going, it's a lot for the social | 11:46 |
| finnb | I know ticketing it would go against the principles but they either need to get a bigger venue or limit the number of people that can go | 11:46 |
| finnb | The Trellis talk last year was great :) | 11:49 |
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| lukego | Software networking room was a bit of a disaster last year. Small room with bad A/V. Most of the people in the room couldn't hear the talk and were only there to hold their seat for one of the other talks coming later. | 12:02 |
| lukego | but that's part of the charm of FOSDEM I suppose :) created a pretty good hallway track | 12:02 |
| lukego | I suppose also that since nobody has name tags your best bet for finding like-minded people is to loiter around outside relevant devrooms and chat to other people who are interested in the topic but couldn't get a seat :) | 12:04 |
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| ZirconiumX | I'm trying to write a Yosys pass, so I may have some dumb-sounding questions because I don't know the codebase very well. | 19:25 |
| ZirconiumX | How do I check if two cell inputs refer to the same signal? | 19:37 |
| mwk | ZirconiumX: just... compare them | 19:40 |
| * ZirconiumX was assuming that operator== was a comparison by value, not by identity | 19:40 | |
| mwk | though the usual approach is to use SigMap to also consider equivalent two wires that are assigned to each other | 19:41 |
| daveshah | This is a pass I wrote that has various signal comparisons using sigmap | 19:41 |
| daveshah | https://github.com/YosysHQ/yosys/blob/master/techlibs/ecp5/ecp5_gsr.cc | 19:41 |
| tpb | Title: yosys/ecp5_gsr.cc at master · YosysHQ/yosys · GitHub (at github.com) | 19:41 |
| daveshah | Although this is for 1 bit signals | 19:42 |
| ZirconiumX | 1-bit is enough for this | 19:42 |
| mwk | ZirconiumX: so how it works is, operator== compares by identity (or by value for const signals) | 19:58 |
| ZirconiumX | Right, I see | 19:59 |
| mwk | but since wires in modules can be assigned to each other (which is represented by module->connections), and you usually want this to be transparent in your passes, the SigMap util is used | 19:59 |
| mwk | you construct a SigMap from a module, and it maps every SigBit to a "canonical" one from the assigned-to-each-other set | 19:59 |
| mwk | then to compare two signals, you do sigmap(a) == sigmap(b) | 19:59 |
| mwk | where sigmap is your pre-constructed SigMap object | 19:59 |
| mwk | and you have to be careful to not invalidate SigMap before you stop using it | 20:00 |
| mwk | (which is not that hard, as long as you don't add/remove connections) | 20:00 |
| * mwk feels the whole thing to be a mess, but eh | 20:01 | |
| * mwk would really love the whole thing to be more SSAish and have a single well-defined instantly-accessible driver for every wire | 20:02 | |
| mwk | gimme LLVM :3 | 20:02 |
| ZirconiumX | Context: I'm writing an ALM packing pass. I realise Yosys is the wrong place to put this, but lacking nextpnr support and Quartus stubbornly refusing Yosys output, I'd like some way of obtaining ALM numbers | 20:03 |
| ZirconiumX | Plus this gives me practice for writing Yosys passes, so | 20:03 |
| ZirconiumX | I feel like the most realistic numbers would come from representing the cells as layers of a tree and then trying to pack each layer | 20:09 |
| mwk | uh what? | 20:11 |
| ZirconiumX | ...This is going to need a diagram, isn't it? | 20:12 |
| mwk | it could help, yes | 20:12 |
| ZirconiumX | https://puu.sh/EXKz0/8537b3a7be.png <-- please suspend your disbelief on the realism of this diagram | 20:16 |
| mwk | I umm | 20:17 |
| mwk | I'm not sure what I'm looking at? | 20:18 |
| ZirconiumX | An example circuit, say from `show`. | 20:18 |
| mwk | there'a a LUT3 with 2 inputs? | 20:19 |
| ZirconiumX | No, the numbers here are reference | 20:19 |
| ZirconiumX | As in "the third LUT" | 20:19 |
| mwk | ahh | 20:19 |
| mwk | alright | 20:19 |
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| ZirconiumX | Now, LUT3 depends on the output of LUT 1, so you might not be able to fuse LUT 3 into LUT 1 | 20:21 |
| ZirconiumX | But you could try to pack LUT 1 and LUT 2 together | 20:21 |
| mwk | why not? | 20:21 |
| mwk | I mean, if they are otherwise fusable? | 20:22 |
| * ZirconiumX sighs and reaches for the output of `show` because apparently this is not realistic enough | 20:22 | |
| ZirconiumX | Note the "might not" there | 20:22 |
| mwk | yes, but why does the fact that LUT 3 depends on LUT 1 matter? | 20:23 |
| mwk | I mean, worse case, you'll just have a path straight from ALM output to its own input? | 20:23 |
| ZirconiumX | I thought combinational loops were a bad thing | 20:24 |
| mwk | they are, but it's not going to be a real combinational loop | 20:24 |
| ZirconiumX | Okay, then clearly I don't know anything here. | 20:29 |
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| dh73 | AFAIK, Quartus/Synplify starts the ALM packing by mapping logic using ALM legal constraints (2 4-input luts, 1 6-output luts, 1 5-input lut + 1 3-input lut, etc), then the Quartus fitter place these instances correctly. I have no deep details honestly, but that's the pattern I've seen. | 20:54 |
| dh73 | For instance; ALUT usage by number of inputs | 20:55 |
| dh73 | 7 input functions 0 | 20:55 |
| dh73 | 6 input functions 0 | 20:55 |
| dh73 | 5 input functions 0 | 20:55 |
| dh73 | 4 input functions 2 | 20:55 |
| dh73 | [=3 input functions 1 | 20:55 |
| ZirconiumX | https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/ug-ag-lab.pdf | 20:55 |
| dh73 | Is packed into 1 ALM (4 input functions 2) | 20:55 |
| ZirconiumX | I sent this paper to mwk, but it's quite useful here too | 20:55 |
| ZirconiumX | I have a rough formula for ALM packing, but I'm looking for generally more realistic numbers. | 20:57 |
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| cznwhale | hello; I am new to yosys - but read the documentation ~80% | 21:32 |
| cznwhale | is it possible to synthetize a design using only toffoli gates? | 21:32 |
| cznwhale | and without any classic gates | 21:33 |
| cznwhale | (nand, nor, not) | 21:33 |
| cznwhale | (toffoli gate are universal reverible gates - and they have 3 in/ 3 out) | 21:33 |
| daveshah | cznwhale: Probably not very well. You can synthesise to arbitrary gate libraries with abc and liberty files but that only maps single output gates | 21:34 |
| daveshah | ie it would only use the final output of the Toffoli gate and not the "route throughs" | 21:35 |
| cznwhale | can you point me in some documentation what is a "gate library"? | 21:36 |
| cznwhale | I tried some experiments | 21:36 |
| cznwhale | if I remove from the liberty file the nor for example (and leave the not and nand) | 21:36 |
| cznwhale | the output netlist will corectly contain only not and nand | 21:36 |
| cznwhale | but if I remove the not | 21:37 |
| cznwhale | an internal error in the abc will pop out | 21:37 |
| daveshah | ABC requires a not gate and a buffer in a liberty file | 21:37 |
| cznwhale | but why this limitation | 21:37 |
| cznwhale | ? | 21:37 |
| cznwhale | a NOT is very simple build with a NAND | 21:38 |
| daveshah | There's no reason, just ABC expecting a typical gate library | 21:38 |
| daveshah | You could always use techmap afterwards to convert the NOT to a NAND | 21:38 |
| daveshah | ie a real world ASIC gate library would always have NOT and buffer cells, and I guess ABC didn't consider more obscure applications | 21:39 |
| cznwhale | so in fact there is no flexibility in the final netlist | 21:39 |
| daveshah | ? | 21:39 |
| cznwhale | I refer that the liberty file does not alow much things to be variable | 21:40 |
| cznwhale | maybe only the names of the gates | 21:40 |
| cznwhale | but not the functions | 21:40 |
| ZirconiumX | You can go add things beyond the gates | 21:40 |
| ZirconiumX | But ABC is fairly limited here because this part of ABC was designed for ASIC synthesis. | 21:41 |
| daveshah | cznwhale: you can have a totally variable set of gates | 21:41 |
| daveshah | There is only one ABC requirement and that is that the set of gates must include not | 21:41 |
| daveshah | The workaround is to use Yosys techmap to convert that not into whatever you want | 21:42 |
| cznwhale | and use extensions for my exotic gate functions, right? | 21:42 |
| daveshah | You don't need to use any extensions | 21:42 |
| daveshah | Standard liberty functions should be fine | 21:43 |
| cznwhale | maybe I didn't understand right the whole flow | 21:43 |
| cznwhale | I saw in the example of synth script | 21:43 |
| cznwhale | that the ABC is called almost the last command | 21:44 |
| daveshah | Yes, that's usually the case | 21:44 |
| cznwhale | (actually the last is an "opt") | 21:44 |
| ZirconiumX | Yosys is a series of passes. You can call any of these passes in whatever order you want | 21:44 |
| daveshah | The previous commands tend to be doing higher level (eg word level) transformations | 21:45 |
| cznwhale | but if I want to have in the final netlist an exotic gate | 21:45 |
| cznwhale | ABC will not handle it | 21:45 |
| daveshah | Then you will probably want techmap after abc to deal with the NOT case | 21:45 |
| cznwhale | I must put some other final command for yosys to do the replacement | 21:45 |
| daveshah | That is "techmap" | 21:46 |
| cznwhale | OK | 21:46 |
| cznwhale | thank you very much! | 21:46 |
| ZirconiumX | ABC is limited to single-output gates. Since I worked on targeting 7400-series logic chips, my solution was a post-processing pass that merged single-output gates into a chip | 21:46 |
| cznwhale | the post-process was your own? | 21:46 |
| ZirconiumX | Yep | 21:46 |
| cznwhale | or a yosys command | 21:46 |
| cznwhale | ok! | 21:47 |
| ZirconiumX | Well, specifically it was pepijndevos' idea; a Python script that operated on the Yosys netlist. | 21:47 |
| cznwhale | :) | 21:47 |
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