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| Duality | hi | 20:27 |
|---|---|---|
| daveshah | hi! | 20:48 |
| Duality | is it correct that i see there is work being done on intel cyclone IV ? | 20:56 |
| Duality | support for that | 20:56 |
| whitequark | cc ZirconiumX | 21:00 |
| mwk | ZirconiumX is working on Cyclone V, not Cyclone IV (and they're quite different things), so unless I'm missing something, it'd be a no | 21:01 |
| ZirconiumX | The CIV is actually dh73's pet project. I have been focusing on the CV/C10GX but it would be possible to do CIV/C10LP if there's sufficient interest (AKA if it would be fun) | 21:02 |
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| ZirconiumX | There *is* some existing support for CIV in synth_intel but my blunt opinion is that synth_intel should be considered untrustworthy. | 21:04 |
| ZirconiumX | As in, I do not trust it to synthesise correctly | 21:04 |
| ZipCPU | ZirconiumX: Cyclone-V w/ ARM? | 21:04 |
| ZirconiumX | ZipCPU: it's the dev board that I have, but by no means the only one I'm targeting | 21:05 |
| ZipCPU | So ... are you targeting with or without the ARM? Just asking, 'cause I have the ARM version ... | 21:05 |
| ZirconiumX | If/when there's a FOSS flow for it, blinky will likely run on WQ's dev board before my own | 21:06 |
| ZirconiumX | ZipCPU: "both" | 21:06 |
| ZipCPU | Ok ... awesome! | 21:06 |
| ZirconiumX | A Cyclone V is a Cyclone V is a Cyclone V. | 21:06 |
| ZipCPU | Ahh ... I remember being told some had ARMs and some did not | 21:07 |
| ZipCPU | The one I have has the ARM on it (DE-10 Nano) | 21:07 |
| mwk | (as opposed to Cyclone 10 which is not necessarily a Cyclone 10) | 21:07 |
| ZirconiumX | Yes, some have a built in ARM core, but fundamentally the FPGA is identical | 21:07 |
| ZipCPU | I look forward to having the opportunity to test something | 21:07 |
| ZirconiumX | mwk: yeah, that's some misguided branding | 21:07 |
| ZipCPU | In the meantime ... I'm still working on the AXI interconnect thing | 21:08 |
| ZipCPU | ... as in, building my own | 21:08 |
| ZipCPU | I'd love to marry this work with the hardware though | 21:08 |
| ZirconiumX | At present I'm trying to get Yosys to target Quartus PnR | 21:08 |
| ZipCPU | Sounds like a good start. I know I was successful doing that with the Max10 | 21:09 |
| ZirconiumX | But given my painful experiences getting even synth_intel_alm to target Quartus, I suspect that the original synthesis script will have bitrotted beyond repair. | 21:10 |
| ZipCPU | Doh! | 21:10 |
| ZirconiumX | Altera chips are curious beasts. | 21:11 |
| ZipCPU | How so? | 21:11 |
| mwk | ZipCPU: considered a Zynq? | 21:11 |
| ZipCPU | mwk: Yep! | 21:11 |
| mwk | at some point I'd love to have FOSS support for it | 21:11 |
| mwk | as in, the parts other than the FPGA proper | 21:11 |
| ZipCPU | I keep considering it, but never jumping in | 21:11 |
| ZirconiumX | As far as I can tell the primitives never considered the possibility of someone trying to create an inverter. | 21:11 |
| ZipCPU | How difficult could an inverter be? | 21:12 |
| mwk | uhh | 21:12 |
| mwk | very | 21:12 |
| ZipCPU | Really? I figured you'd just adjust the inputs to the LUT it was heading into | 21:12 |
| mwk | you can have inverters on other things than LUT inputs/outputs | 21:13 |
| ZirconiumX | ZipCPU: each PIP in an Altera platform is inverting, so inversion is performed by PIP parity. | 21:13 |
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| mwk | yah | 21:13 |
| ZipCPU | Seriously? Not sure why you'd do that. It just makes the book-keeping nasty | 21:13 |
| mwk | ZipCPU: because a CMOS inverter is cheaper than a CMOS buffer | 21:13 |
| ZipCPU | Then again ... I've never built one of these, so I wouldn't be certain why you do much of any of this | 21:13 |
| mwk | Xilinx Ultrascale does the same | 21:13 |
| ZipCPU | Ah, ok | 21:14 |
| mwk | so if you're routing to a LUT input, or some other input with a free inversion, you can take any path | 21:14 |
| mwk | but if you're routing to some other input (eg. FF reset or clock enable), you get to choose a route with the right parity | 21:14 |
| mwk | a fun puzzle for the router | 21:14 |
| ZipCPU | ... or stuff a LUT into the puzzle | 21:14 |
| ZipCPU | Yeah | 21:15 |
| ZirconiumX | The router which I should mention is *still* based on VPR | 21:15 |
| ZipCPU | There exists one based upon VPR? That's something | 21:15 |
| ZirconiumX | Yep, the Quartus router is built on VPR | 21:15 |
| ZirconiumX | Not that they open sourced any of their modifications | 21:15 |
| whitequark | wow, really? | 21:16 |
| ZirconiumX | Mhm. | 21:16 |
| * ZipCPU ditto's whitequark's response, wow, really? | 21:17 | |
| ZirconiumX | I always wondered why Quartus took so long to start. Turns out loading in 160-ish shared libraries at startup takes a while. | 21:17 |
| ZipCPU | I thought it was nothing more than the bloat common to almost all GUI software these days | 21:19 |
| whitequark | have they heard of prelinking? | 21:19 |
| whitequark | actually | 21:19 |
| whitequark | you can just prelink them yourself, try it | 21:19 |
| whitequark | apt-get install prelink | 21:19 |
| ZirconiumX | But within those libraries (which have symbols in release code I should point out), you can find VPR function names | 21:19 |
| whitequark | (and turn off ASLR of course) | 21:19 |
| ZirconiumX | Additionally, Sarayan figured out the database formats | 21:20 |
| ZirconiumX | It's essentially a tag length value stream where they just dump struct values in binary | 21:21 |
| ZirconiumX | Good thing they chose to tag them with the struct name *in plain text* | 21:21 |
| mwk | convenient | 21:21 |
| ZirconiumX | Although I'm not awarding points for the 7-layer nested recursive template. | 21:22 |
| whitequark | lmao | 21:22 |
| whitequark | is that like a mangled c++ name? | 21:22 |
| ZirconiumX | Nope, unmangled | 21:22 |
| mwk | wait what | 21:23 |
| ZirconiumX | I have the horrible suspicion that somebody went to the trouble of hardcoding these type names into the binary. | 21:23 |
| ZirconiumX | Alternatively Quartus unmangles its own symbol table to resolve these | 21:24 |
| ZirconiumX | Which is also possible | 21:24 |
| ZipCPU | Whoa | 21:24 |
| ZipCPU | So the databases have been reverse engineered ? | 21:25 |
| ZirconiumX | (I know it has this capability because you get stack traces on ICEs with full function names) | 21:25 |
| ZirconiumX | ZipCPU: the format has, but not the data (as of yet) | 21:25 |
| mwk | ZipCPU: layers are being slowly peeled off | 21:25 |
| ZipCPU | Oh, okay ... still worth noting | 21:25 |
| ZirconiumX | My understanding is that Sarayan is trying to get the bitstream data done by reversing the bitstream databases | 21:26 |
| ZirconiumX | My major question here is that if we develop something that reads the Quartus databases we're going to be in the interesting quandary of needing Quartus to not use Quartus. | 21:27 |
| ZipCPU | Don't ask me. IANAL | 21:28 |
| ZipCPU | ;) | 21:28 |
| ZirconiumX | It also means we've got to link in both liblzma and zlib because Quartus uses those interchangeably. | 21:28 |
| ZirconiumX | (mmm, software bloat) | 21:29 |
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| ZirconiumX | Now, does anybody have any more questions? | 21:31 |
| ZirconiumX | If not, I'll go back to sleep :P | 21:31 |
| ZipCPU | No more questions, just looking forward to fun and exciting results ;) | 21:31 |
| mwk | please don't tell me mentioning you on IRC actually wakes you up :p | 21:31 |
| ZirconiumX | *buzz buzz* | 21:31 |
| ZipCPU | Oh, dear. Sorry. Do go and get some sleep. | 21:32 |
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| corecode | haha | 21:37 |
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| ZirconiumX | Well I feel a bit better now at least | 22:26 |
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