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| promach3 | Is it possible to simulate and synthesize and generate bitstream from https://github.com/aws/aws-fpga/blob/master/hdk/common/shell_v04261818/design/sh_ddr/sim/sh_ddr.sv ? | 06:28 |
|---|---|---|
| tpb | Title: aws-fpga/sh_ddr.sv at master · aws/aws-fpga · GitHub (at github.com) | 06:28 |
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| rjeli | hello! got an icebreaker @ ccc yesterday & in love | 15:55 |
| rjeli | y’all are amazing, foss fpga is amazing | 15:55 |
| OK_b00m3r | rjeli: o/ | 15:57 |
| ZipCPU | o/ | 16:04 |
| klotz | Yeah got one as well | 16:08 |
| klotz | Hands down my best investment this year | 16:08 |
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| meawoppl | Alright, I have another strange bug to report | 20:32 |
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| meawoppl | rather I don't know if it is a bug or verilog "feature" | 20:33 |
| meawoppl | yosys appears to support synthesizing case statements where the labels aren't defined | 20:33 |
| meawoppl | localparam[3:0] START = 0, FRAME_START = 1, FRAME_END = 2, IGNORE = 3, LONGPACKET = 4, UNKNOWN = 10, DONE = 15; reg[3:0] state = START; | 20:33 |
| meawoppl | case(state) | 20:34 |
| meawoppl | FOO: whatever | 20:34 |
| meawoppl | endcase | 20:34 |
| meawoppl | compiles | 20:34 |
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| daveshah | I think this is a Verilog oddity | 20:47 |
| daveshah | case statements allow signals as labels | 20:48 |
| daveshah | and undefined signals default to a 1 bit wire (without `default_nettype) | 20:48 |
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| daveshah | You should at least get a warning like `Warning: Identifier `\FOO' is implicitly declared.` | 20:50 |
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| meawoppl | oui, that seems fraught imho, signals as labels seems a little generally hairy, but I can see how it could be used.... | 20:56 |
| meawoppl | is there any way to have yosys promote warnings to errors? | 20:57 |
| meawoppl | My general experience there is that warnings are more likely than not errors of some variety | 20:57 |
| meawoppl | (but as advertised, I am a verilog n00b) | 20:57 |
| meawoppl | Also I feel like I should send you a bottle of whisky for how helpful you have been daveshah | 21:01 |
| daveshah | You can do ` -e regex` to turn warnings matching a regex into an error | 21:02 |
| daveshah | In this case the best option is to add "`default_nettype none" at the top of your file | 21:03 |
| daveshah | This will prevent any implicit signals from being created | 21:03 |
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| devik2 | ZipCPU, can I ask about your f_past_valid usage ? | 22:45 |
| ZipCPU | Sure, what's your question? | 22:46 |
| devik2 | what's difference from $initstate ? | 22:46 |
| ZipCPU | Probably just that I've never used $initstate ;) | 22:46 |
| ZipCPU | But seriously, I'd need to look it up to know | 22:46 |
| devik2 | ahh .. I started to learn from your blog and I then found this one and it seems to do the same :-) | 22:47 |
| devik2 | btw, I tried to understand how to verify whole simple MCU, I just created extra simple one as one case() - all in one cycle, no pipelining, | 22:48 |
| ZipCPU | Ok, go on | 22:49 |
| devik2 | then fully pipelined one with bypasses etc.. | 22:49 |
| devik2 | and proved they have the same output for any input code (coded as $anyconst) | 22:49 |
| ZipCPU | I should point out ... I'm still very much the learner myself. I've only been doing formal types of stuffs since ... October, 2017 | 22:49 |
| devik2 | it seems to work, I proved it for 20 cycles and any 8 instruction code | 22:50 |
| ZipCPU | Awesome! How about induction? | 22:50 |
| devik2 | not yet :-( | 22:50 |
| devik2 | I think, is ever possible to do sequntioal equivalence as induction ? | 22:51 |
| devik2 | it seems as too complex task | 22:51 |
| ZipCPU | Might depend upon the core | 22:52 |
| devik2 | interestingly, yosys "sat" command is sometimes faster in proving than yosys-smt | 22:52 |
| ZipCPU | Sorry, but .... I'm going to need to step away here. Perhaps we can continue later? | 22:52 |
| devik2 | yeah that ok, | 22:53 |
| devik2 | I have to ho to sleep, it is 23PM here | 22:53 |
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