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| meawoppl | followup, is bitrange assigment like this legit | 01:19 |
|---|---|---|
| meawoppl | reg[15:0] foo; | 01:19 |
| meawoppl | posedge @(whatever) | 01:19 |
| meawoppl | foo[15:8] <= foo[7:0]; | 01:19 |
| meawoppl | ? | 01:19 |
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| ZipCPU | meowppl: Yes, that's a legitimate assignment. I like to place the assignment to foo[7:0] nearby, but it can be done in a separate block | 01:31 |
| ZipCPU | (Verilator might have problems with separate blocks for separate parts of a value, but it is legal Verilog) | 01:31 |
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| Xiretza | I can't get synth_xilinx to infer true dual port RAMs (two read and write ports, one of each per clock domain), is that simply not supported yet? | 20:34 |
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| whitequark | yes | 20:37 |
| whitequark | yosys can't do TDP RAM at all yet | 20:37 |
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| Xiretza | ooooh, I see, that explains it. I guess it was never necessary for ICE40/ECP5 | 20:38 |
| daveshah | It is necessary for ECP5 | 20:38 |
| daveshah | It's just memory_bram is too horrible for anyone to have attempted to do it yet | 20:38 |
| Xiretza | that doesn't exactly inspire confidence in trying it myself... to be clear, most configurations with just a single clock domain should be possible, just not two independent clocks per $mem? | 20:42 |
| mwk | Xiretza: no | 20:44 |
| mwk | the problem is that yosys doesn't know how to merge a single port in both read and write modes | 20:45 |
| mwk | *how to use | 20:45 |
| mwk | so if you read from memory in one place, and write to it in another place, it has to use two different ports | 20:46 |
| Xiretza | mwk: and yosys only supports a single port per memory? | 20:47 |
| mwk | no | 20:49 |
| mwk | it supports however many ports are available | 20:49 |
| mwk | just every available port can only be either read or write, not both at once | 20:49 |
| Xiretza | mwk: okay, and how do those relate to clock domains? do all ports have to be on the same clock? | 20:50 |
| mwk | clock domains don't matter, it's about ports | 20:54 |
| mwk | the two ports can be on two different clocks, and yosys does support that | 20:54 |
| Xiretza | so it can only use each of the two ports a RAMB36E1 offers as either read or write (so read+read, read+write, or write+write, only one of which makes sense)? | 20:57 |
| mwk | correct | 20:57 |
| daveshah | read-read would make sense for a ROM | 20:57 |
| daveshah | but it's not supported | 20:57 |
| mwk | huh, it's not? | 20:58 |
| daveshah | I don't think so, it would need an extra rule for memory_bram | 20:58 |
| mwk | ugghh | 20:58 |
| mwk | right | 20:58 |
| mwk | of course | 20:58 |
| daveshah | memory_bram itself should support such a pattern | 20:58 |
| Xiretza | daveshah: right, are those built from RAMB36E1 though? | 20:58 |
| daveshah | but the rules and techmaps don't | 20:58 |
| daveshah | Xiretza: yes or RAMB18E1 for smaller ones | 20:58 |
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| Xiretza | interesting, for some reason I thought there were separate ROM blocks. alright then, seems like some more in-depth work is required, don't think I have much of a chance to take that on. I'll just keep the designs I'm testing to two ports for now | 21:01 |
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| mwk | ROM is just preinitialized RAM with the ports used only for read | 21:02 |
| Xiretza | yeah, it makes sense now that I think about it, just never occured to me | 21:03 |
| Xiretza | thanks a lot for all your help! | 21:03 |
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