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| ZirconiumX | dh73: You've got an Arria 10GX, right? | 18:26 |
|---|---|---|
| dh73 | Yes | 18:26 |
| ZirconiumX | Do you use Quartus for synthesis, or Yosys? | 18:26 |
| ZirconiumX | dh73: ^ | 18:29 |
| dh73 | For the Arria 10, I ran few experiments using Yosys in the past, but not right now since Quartus Pro have changed a lot of things compared with Standard. I was seeing some issues with memory mapping, and since Quartus Pro have removed most of the cdb commands (like write vqm, since they don't support it in Pro, but a new QDB format or something like that), I stopped. I have a local branch with some arria 10 functionality, yet is incomplet | 18:33 |
| dh73 | e | 18:33 |
| ZirconiumX | You can get VQM-like with quartus_eda | 18:33 |
| ZirconiumX | If you export it for simulation you get a netlist out | 18:33 |
| ZirconiumX | I have a C10GX branch, but I don't think A10GX would be difficult to add, except for timing information | 18:34 |
| dh73 | Right, have you tried to read the VQM back in latest version?, back in 2017 that was not possible because VQM support have been decreased in Pro, and some parsing issues was present at that time. I've been using Synplify netlist example as base. Moved to Pro because Standard create congestion a lot of times, but Standard is faster in getting the bitstream | 18:40 |
| dh73 | This blogger had similar issues http://billauer.co.il/blog/2018/02/intel-fpga-altera-qxp-qdb-standard-pro/ | 18:41 |
| tpb | Title: QDB vs. QXP, Quartus Pro vs. Standard: Post-synthesis packaging of an IP core (at billauer.co.il) | 18:41 |
| ZirconiumX | dh73: At present no | 18:44 |
| dh73 | it might be worth checking it | 18:47 |
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| ZirconiumX | daveshah: What did you base the abc9 -W timing figures on? Obviously it's a fudge factor, but is it based on anything specific? | 19:08 |
| daveshah | It's a number that gives a decent Fmax/area tradeoff, tbh | 19:09 |
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