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| meawoppl | greeting humans | 02:05 |
|---|---|---|
| meawoppl | anyone around in here? | 02:05 |
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| meawoppl | anyone alive? | 02:40 |
| meawoppl | I am looking for some help with nextpnr, does this channel do that? | 02:40 |
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| meawoppl | When I get assertion failures in nextpnr, is this the place to talk about them? | 03:20 |
| sorear | either here or ##openfpga | 03:45 |
| sorear | but if you can’t stay online for more than 50 minutes you may have better luck with email or github issues | 03:47 |
| sorear | idk who else is awake at this hour | 03:47 |
| ZipCPU | At least the channel is recorded, so there is a chance he might see that someone responded to him | 03:53 |
| meawoppl | I'll give it a go tomorrow AM when i reboot into linux again, until then i am stuck with the windows toolchain :/ | 03:53 |
| sorear | Nearly certain nextpnr supports Windows | 04:28 |
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| meawoppl | so, if I am having an assertion fault in nextpnr, what do I share to reproduce it? a .json and the flags I used? | 14:27 |
| meawoppl | I basically seem to seg-fault nextpnr anytime I use a module with parameters | 14:27 |
| ZirconiumX | What are you using to synthesise for nextpnr? Yosys, right? | 14:29 |
| meawoppl | yosys, yes | 14:29 |
| ZirconiumX | Given that using a module with parameters is amongst the most common Verilog operation, I suspect it's not the problem here | 14:30 |
| ZirconiumX | The JSON, the assertion error, that command lines of both Yosys and Nextpnr and possibly the input HDL | 14:31 |
| meawoppl | gotcha, I will reboot into linux land in a bit post those here | 14:32 |
| meawoppl | they are specifically related to the ice40 builtin modules (tristate buffers and led driver) if that helps any | 14:33 |
| ZirconiumX | Not as such | 14:33 |
| whitequark | are your nextpnr and yosys up-to-date? | 14:34 |
| meawoppl | yeah, I built both from source this week | 14:34 |
| meawoppl | I also made a .deb for nextpnr, and I am tempted to roll a ppa for all these tools to make them apt friendy | 14:35 |
| meawoppl | aiit, power-cycling to linux, brb | 14:38 |
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| meawoppl | heyo, I got caught in windows update land :/ | 14:52 |
| meawoppl | aiiit, so I am invoking yosys as the following: | 14:53 |
| meawoppl | `yosys -s integrate.ys` | 14:53 |
| meawoppl | the script has only a few lines: | 14:53 |
| meawoppl | ``` | 14:53 |
| meawoppl | ` | 14:54 |
| meawoppl | `read_verilog source/impl_1/*.vsynth_ice40 -top top -blif magicschoolbus.blifwrite_json magicschoolbus.json` | 14:54 |
| meawoppl | bah, that is getting munged: | 14:54 |
| meawoppl | `read_verilog source/impl_1/*.v` | 14:54 |
| meawoppl | `synth_ice40 -top top -blif magicschoolbus.blif` | 14:54 |
| meawoppl | `write_json magicschoolbus.json` | 14:54 |
| meawoppl | that is all ^^ | 14:55 |
| meawoppl | when I run nextpnr I call the following: | 14:55 |
| meawoppl | `nextpnr-ice40 --up5k --package sg48 --json magicschoolbus.json --pcf pins.pcf --asc output.asc` | 14:56 |
| meawoppl | the output looks like this: | 14:56 |
| meawoppl | https://gist.github.com/meawoppl/da2d6b4a6804eba28f3df25cb5b899c5 | 14:57 |
| ZirconiumX | meawoppl: Why not just `yosys -p "synth_ice40 -top top -json magicschoolbus.json" source/impl_1/*.v`? | 14:57 |
| tpb | Title: nextpnr bug? · GitHub (at gist.github.com) | 14:57 |
| ZirconiumX | That seems a bit simpler :P | 14:57 |
| meawoppl | yeah that is better | 14:58 |
| ZirconiumX | daveshah: ^ | 14:58 |
| whitequark | can you show the code? | 14:58 |
| daveshah | Yeah this is obviously a bug | 14:58 |
| meawoppl | whitequark I don't think I can share it without stripping a bunch of material | 15:01 |
| meawoppl | the observation I wanted to put forward is that if I take the parameters out of the ice40 modules the pnr call succeeds, which I find interesting | 15:01 |
| daveshah | No one will fix it without the code | 15:02 |
| meawoppl | kk, let me try to make a minimal repro | 15:02 |
| meawoppl | eta ... 5 or so? | 15:05 |
| meawoppl | also, thanks! | 15:05 |
| meawoppl | alright, that was much easier than I thought to strip down | 15:10 |
| meawoppl | making it 1-command reproduction | 15:10 |
| meawoppl | https://github.com/meawoppl/nextpnr-bug-repro/tree/master | 15:17 |
| tpb | Title: GitHub - meawoppl/nextpnr-bug-repro: Not much to this all (at github.com) | 15:17 |
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| meawoppl | @da | 15:18 |
| meawoppl | daveshah, if you clone the above and run `reproduce.sh` it should show the problem I am having | 15:18 |
| daveshah | Having a look now | 15:19 |
| daveshah | meawoppl: https://github.com/meawoppl/nextpnr-bug-repro/blob/master/LedController.v#L39-L42 should be strings like "0b1" | 15:20 |
| tpb | Title: nextpnr-bug-repro/LedController.v at master · meawoppl/nextpnr-bug-repro · GitHub (at github.com) | 15:20 |
| daveshah | this is silly but it is for compatibility with the Lattice tools | 15:20 |
| daveshah | let me add a better error though | 15:20 |
| meawoppl | oh, are parameter literals treated strangely somehow? | 15:23 |
| daveshah | yes | 15:23 |
| daveshah | this is very specific to the UltraPlus primitives | 15:23 |
| daveshah | the SiliconBlue era primitives (LUTs, RAMs, SB_IO, PLLs) don't do this - only the LED driver and UltraPlus hard IPs do | 15:24 |
| meawoppl | gotcha, howabout the high-freq osc? | 15:24 |
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| daveshah | that's string style too | 15:25 |
| meawoppl | woah, I think it all just worked..... | 15:31 |
| meawoppl | thanks so much daveshah | 15:31 |
| meawoppl | how can I contribute to this project? It is going to save me a ton of time I can already tell | 15:31 |
| corecode | hi | 15:31 |
| daveshah | meawoppl: first step is to keep the issue reports coming :) (I've just improved the error message in this case) | 15:32 |
| daveshah | also have a look at open Yosys/nextpnr issues | 15:32 |
| daveshah | hi corecode! | 15:32 |
| corecode | hi dave | 15:32 |
| corecode | you coming to congress this year? | 15:32 |
| daveshah | no, I won't be | 15:32 |
| corecode | boo | 15:32 |
| corecode | last year there were a lot of people doing icebreaker tutorials | 15:33 |
| meawoppl | is that the one in Munich? | 15:33 |
| corecode | leipzig | 15:33 |
| corecode | are there any ultra bugs that need attention? | 15:34 |
| daveshah | Not sure, I have not tried the ultra support myself | 15:34 |
| corecode | i am using it | 15:34 |
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| meawoppl | daveshah, one other question if you have some bandwidth | 15:41 |
| daveshah | sure | 15:42 |
| meawoppl | what is the right way to do a bidirectional pin (read and write) where the "high" needs to be high-impedance? (already has external pullup) | 15:43 |
| corecode | instantiate a pin gpio instance and change OE | 15:44 |
| daveshah | What you have looks alright to me | 15:44 |
| daveshah | oh yeah, you can just have the output data set to 1'b0 as corecode | 15:45 |
| daveshah | says | 15:45 |
| daveshah | I did this for I2C a while ago | 15:46 |
| daveshah | https://github.com/SymbioticEDA/MARLANN/blob/master/demo/camera/cameraif.v#L114-L137 | 15:46 |
| tpb | Title: MARLANN/cameraif.v at master · SymbioticEDA/MARLANN · GitHub (at github.com) | 15:46 |
| corecode | yep looks like what i suggested | 15:48 |
| corecode | would be nice if you could express this in verilog and reliably get the right IO instantiated | 15:48 |
| meawoppl | corecode and daveshah thanks for the leads | 15:56 |
| meawoppl | can I keep pestering this channel with veriolog questions? | 15:56 |
| corecode | i guess | 15:58 |
| corecode | there is also ##verilog and ##fpga | 15:58 |
| corecode | ymmv | 15:58 |
| ZirconiumX | Also ##openfpga | 16:07 |
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| meawoppl | thanks! | 16:27 |
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| steeeels | Hi all, I have rather silly question and tbh it's more verilator related one, but still. Could anyone tell me if there's something wrong with this piece of code: https://pastebin.com/w6fWKUfa The reason I'm asking is that it works 100% fine if I pass --public option to verilator and doesn't work w/o it. | 17:31 |
| tpb | Title: [VeriLog] module lfsr_rnd #( parameter POLY = 32'h80200003 ) ( input wire - Pastebin.com (at pastebin.com) | 17:31 |
| whitequark | seems fine to me. how does it break? | 17:32 |
| steeeels | In case I run verilator w/o --public option, every signal is zero, except POLY of course, please check these screenshots: https://imgur.com/a/A3hZtJo | 17:35 |
| tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 17:35 |
| steeeels | The generated c++ code by verilator looks more or less similar, at least for those signals. It's hard to tell for sure for 10k lines of code | 17:39 |
| whitequark | it generates 10kloc for that one module? | 17:42 |
| steeeels | Nope. The SoC generates 10k LOC, but the issue is with lfsr module. | 17:44 |
| whitequark | are you sure there is a problem in lfsr module and not something else? | 17:45 |
| whitequark | it might be visible in the lfsr module but have its cause elsewhere | 17:45 |
| steeeels | I believe so, yes. At least the code executes unless it tries to read something non-zero from random generator, which in this case is impossible. I'll try to minimize the reproduction and create a topic on veripool | 17:48 |
| steeeels | Thanks | 17:52 |
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