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| ZirconiumX | https://github.com/YosysHQ/yosys/issues/1531 <-- While this is probably a Yosys bug, this feels like enough of a corner case that it could equally be Verilog. | 12:05 |
|---|---|---|
| tpb | Title: Assignment of 0 to for loop variable leads to a 1 in MSB · Issue #1531 · YosysHQ/yosys · GitHub (at github.com) | 12:05 |
| ZirconiumX | Or maybe my Verilog knowledge just sucks | 12:05 |
| mwk | hmm | 12:10 |
| mwk | FWIW i[1:1] evaluates to 1'bx here (in yosys), not 1'b1 | 12:11 |
| mwk | okay, so the AST looks reasonable before simplification and already has 1'bx after simplification | 12:21 |
| mwk | simplify.cc, 3769 LOC | 12:21 |
| mwk | am I brave enough... | 12:21 |
| mwk | oh heh | 12:25 |
| mwk | okay, I think I see the bug | 12:25 |
| mwk | line 1191: I'm reasonably sure we should be converting the value to the target register's width | 12:26 |
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