*** tpb has joined #yosys | 00:00 | |
*** klotz has quit IRC | 00:56 | |
*** rohitksingh has quit IRC | 02:10 | |
*** rohitksingh has joined #yosys | 03:10 | |
*** nrossi has joined #yosys | 04:40 | |
*** citypw has joined #yosys | 05:00 | |
*** _whitelogger has quit IRC | 05:33 | |
*** _whitelogger has joined #yosys | 05:35 | |
*** rohitksingh has quit IRC | 05:43 | |
*** rohitksingh has joined #yosys | 05:44 | |
*** cr1901_modern has quit IRC | 07:11 | |
*** emeb_mac has quit IRC | 07:20 | |
*** cr1901_modern has joined #yosys | 07:43 | |
*** dys has joined #yosys | 10:16 | |
*** Jybz has joined #yosys | 10:28 | |
*** kraiskil has joined #yosys | 10:52 | |
*** rohitksingh has quit IRC | 10:55 | |
*** kraiskil has quit IRC | 11:18 | |
*** kraiskil has joined #yosys | 11:29 | |
*** dys has quit IRC | 11:34 | |
*** rohitksingh has joined #yosys | 11:38 | |
*** kraiskil has quit IRC | 11:59 | |
*** rohitksingh has quit IRC | 12:42 | |
*** kraiskil has joined #yosys | 12:55 | |
*** _whitelogger has quit IRC | 13:54 | |
*** _whitelogger has joined #yosys | 13:56 | |
*** flaviusb has quit IRC | 14:02 | |
*** citypw has quit IRC | 16:03 | |
*** fsasm has joined #yosys | 16:13 | |
*** gmc has quit IRC | 17:29 | |
*** kraiskil has quit IRC | 17:40 | |
*** cr1901_modern has quit IRC | 17:57 | |
*** gmc has joined #yosys | 17:59 | |
*** kraiskil has joined #yosys | 18:33 | |
*** fsasm has quit IRC | 18:33 | |
*** cr1901_modern has joined #yosys | 18:50 | |
*** ravenexp has quit IRC | 19:08 | |
*** ravenexp has joined #yosys | 19:12 | |
*** bobzoidting has joined #yosys | 19:13 | |
bobzoidting | I have a question about synthesis in general , probably not specific to yosys. Is it best practice to try and minimize the number of states in a statemachine or not? Will adding states instead of using combinational logic within states increase the logic size? | 19:14 |
---|---|---|
bobzoidting | One example is, lets' say I have a statemachine to serialize RGB colours in 8bit/8bit/8bit format onto a serial bus for LEDs, does it make sense to separate these out the colours into states. I.E a Red colour state, Green colour state or Blue colour state | 19:17 |
*** kraiskil has quit IRC | 19:59 | |
*** kraiskil has joined #yosys | 20:00 | |
*** rohitksingh has joined #yosys | 20:19 | |
*** kraiskil has quit IRC | 20:23 | |
*** kraiskil has joined #yosys | 20:31 | |
*** emeb_mac has joined #yosys | 20:52 | |
janrinze | daveshah: ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries. What does this mean? | 21:00 |
daveshah | It's just an ABC thing | 21:01 |
daveshah | I think it means a connection between a carry chain and other logic | 21:01 |
daveshah | It's not actually a problem of any kind, I don't know why it's a warning and not just a message | 21:01 |
janrinze | daveshah: thanks. the design works well, no issues. | 21:02 |
janrinze | daveshah: I've just added a floating point copro to my cpu. was quite a bit of fiddling to get it right but it works now. It still surprises me how well Yosys can convert complex verilog statements into something that runs quite fast. | 21:04 |
*** Jybz has quit IRC | 21:05 | |
*** kraiskil has quit IRC | 21:21 | |
*** nrossi has quit IRC | 21:27 | |
bobzoidting | It's pretty cool how much you can do now with free toolchains | 21:35 |
bobzoidting | and for $10 you can build a custom RISCV MCU in a few hours with a custom peripheral | 21:36 |
janrinze | bobzoidting: Indeed. And the tools get better every day. | 21:36 |
bobzoidting | yeah, free RISCV implementations with free synthesis tools and free compilers..You can do so much so easily | 21:40 |
*** rohitksingh has quit IRC | 21:50 | |
*** bobzoidting has quit IRC | 22:01 | |
*** rohitksingh has joined #yosys | 22:23 | |
*** X-Scale has quit IRC | 22:41 | |
*** X-Scale` has joined #yosys | 22:41 | |
*** X-Scale` is now known as X-Scale | 22:42 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!