Sunday, 2019-11-17

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bobzoidtingI have a question about synthesis in general , probably not specific to yosys. Is it best practice to try and minimize the number of states in a statemachine or not? Will adding states instead of using combinational logic within states increase the logic size?19:14
bobzoidtingOne example is, lets' say I have a statemachine to serialize RGB colours in 8bit/8bit/8bit format onto a serial bus for LEDs, does it make sense to separate these out the colours into states. I.E a Red colour state, Green colour state or Blue colour state19:17
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janrinzedaveshah: ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries.   What does this mean?21:00
daveshahIt's just an ABC thing21:01
daveshahI think it means a connection between a carry chain and other logic21:01
daveshahIt's not actually a problem of any kind, I don't know why it's a warning and not just a message21:01
janrinzedaveshah: thanks. the design works well, no issues.21:02
janrinzedaveshah: I've just added a floating point copro to my cpu. was quite a bit of fiddling to get it right but it works now. It still surprises me how well Yosys can convert complex verilog statements into something that runs quite fast.21:04
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bobzoidtingIt's pretty cool how much you can do now with free toolchains21:35
bobzoidtingand for $10 you can build a custom RISCV MCU in a few hours with a custom peripheral21:36
janrinzebobzoidting: Indeed. And the tools get better every day.21:36
bobzoidtingyeah, free RISCV implementations with free synthesis tools and free compilers..You can do so much so easily21:40
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