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| pepijndevos | Why is there a $PACKER_VCC and $PACKER_GND in my Nextpnr generic output? They got mapped to a slice with a LUT INIT of 1 and 0, as integers, while all other LUT have binary strings as init. | 09:08 |
|---|---|---|
| daveshah | They are for driving 0 and 1 as needed | 10:00 |
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| pepijndevos | daveshah, right, but on Gowin ther is just a global VCC and VSS net, can I express that somehow? | 10:52 |
| daveshah | You could modify the packer to create a single cell with two pins instead, one for the Vcc net and one for the Vss net | 10:53 |
| daveshah | and use that instead of the LUTs | 10:53 |
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| pepijndevos | omg, I can make a Gowin bitstream! I just need to add constraints. Does the generic target have a way to do that? I can probably find this... | 17:26 |
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| daveshah | pepijndevos: you can either manually instantiate IO buffers and set the BEL attribute on them; or hack something in Python to set the BEL attribute on cells | 17:35 |
| daveshah | I would recommend the former | 17:36 |
| pepijndevos | Hm okay, but how does that interact with reading a netlist? | 17:37 |
| daveshah | Effectively, don't have any top level ports in your netlist | 17:37 |
| daveshah | Just IO buffer cells instantiated with the BEL=... and keep=1 attributes set | 17:37 |
| daveshah | I have an example somewhere, let me dig it out | 17:38 |
| daveshah | This is for Xilinx but same principle applies elsewhere | 17:39 |
| daveshah | https://www.irccloud.com/pastebin/zNZXuyyv/ | 17:39 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 17:39 |
| daveshah | (you would need blackbox definitions for the IO buffer primitives too) | 17:39 |
| pepijndevos | Oh! On the verilog side. Interesting. | 17:40 |
| pepijndevos | Nice, thanks | 17:40 |
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| janrinze | will 'autoname' add more comprehension for ecp5 too? | 18:35 |
| janrinze | i see it's added for synt_ice40 but it could easily be added to synth_ecp5 too, right? | 18:36 |
| janrinze | i just answered my own question. Added the run("autoname"); to the if (check_label("check")) and apparently it works okay. | 20:10 |
| janrinze | Also give a lot more sensible info about the critical path now. Nice. | 20:11 |
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| daveshah | janrinze: yeah | 20:55 |
| daveshah | I'll apply that now | 20:56 |
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| daveshah | janrinze: done | 21:03 |
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| janrinze | daveshah: can we improve the memory implementation? somehow it's near impossible to have a large dual port memory inferred. I have a solution that works with manually setting up lots of DP16KD but initializing that with a file is quite a challenge. | 21:55 |
| daveshah | It needs a total rewrite and that's a big project | 21:56 |
| janrinze | hmm.. it does? | 21:56 |
| janrinze | What if we do things incrementally? | 21:57 |
| ZirconiumX | daveshah: it's the memory_bram pass, right? | 21:58 |
| daveshah | Yeah, don't even look at the code | 21:58 |
| daveshah | It has been the source of several horrible synthesis bugs too | 21:59 |
| janrinze | It is possible to have MemoryA correctly inferrred with DP16KD. | 22:00 |
| janrinze | Thus we can inferr two seperate memory blocks with DP16KD. which are unrelated. | 22:00 |
| janrinze | now if we use the access ports of the second and tie them to the first, discarding the second blocks, we should have a working DPRAM | 22:01 |
| janrinze | right? | 22:01 |
| janrinze | Or does the default implementation use both ports? | 22:02 |
| janrinze | if the address for reading and writing of memA uses the same wires we can guarantee that only one port is sufficient. | 22:04 |
| janrinze | thus implying that if the same is true for memB we can safely assume that each can be mapped to a single port of the DP16KD respectively. | 22:05 |
| janrinze | Right? | 22:05 |
| daveshah | This is all technically correct | 22:07 |
| daveshah | But memory_bram is a hacky enough pass already | 22:08 |
| janrinze | I can feel a big "But..." coming.. | 22:08 |
| daveshah | And personally I'm not interested in adding any more hackyness or time wasting missynthesis bugs to a pass that really needs reconsideration | 22:08 |
| janrinze | makes sense. | 22:08 |
| daveshah | Particularly given there are several other missing features like async bram, a better transparency model and resets | 22:09 |
| daveshah | Better handling of transparent ports, in particular, is needed for support for common dpram patterns | 22:09 |
| janrinze | Okay, understood. | 22:09 |
| janrinze | Since i already have a module written to use DP16KD directly, I would like to find a way to set it up using initial $readmemh("rom_memory.hex",memory); | 22:11 |
| janrinze | because I am pretty sure that this readmemh wont work on a module. :-D | 22:11 |
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