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| pepijndevos | Yuk, ifs without brackets. Does Nextpnr have a code style guide? | 08:49 |
|---|---|---|
| whitequark | https://github.com/YosysHQ/nextpnr/blob/master/.clang-format | 08:51 |
| tpb | Title: nextpnr/.clang-format at master · YosysHQ/nextpnr · GitHub (at github.com) | 08:51 |
| pepijndevos | oh wowie, I can tell llvm to yell at me and reformat stuff, right? | 08:52 |
| pepijndevos | https://github.com/YosysHQ/nextpnr/blob/master/CMakeLists.txt#L296 | 08:53 |
| tpb | Title: nextpnr/CMakeLists.txt at master · YosysHQ/nextpnr · GitHub (at github.com) | 08:53 |
| pepijndevos | yes | 08:53 |
| whitequark | clang but yes (it's a different project) | 08:53 |
| pepijndevos | neat | 08:55 |
| daveshah | Also have a look at https://github.com/YosysHQ/nextpnr/blob/master/docs/coding.md which is some higher level tips | 08:58 |
| tpb | Title: nextpnr/coding.md at master · YosysHQ/nextpnr · GitHub (at github.com) | 08:58 |
| pepijndevos | It didn't remove brackets from my single-line ifs though, so I suppose both are fine. | 08:58 |
| pepijndevos | Oh nice, I had seen most of the "see also" ones, but not this one yet. | 08:59 |
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| daveshah | Check https://github.com/YosysHQ/nextpnr/blob/master/docs/netlist.md if you haven't seen it too | 09:02 |
| tpb | Title: nextpnr/netlist.md at master · YosysHQ/nextpnr · GitHub (at github.com) | 09:02 |
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| pepijndevos | What is the intention of the generic target? Seems very tempting for a PoC to just hack a few dozen lines of Python rather than thousands of lines of C. But maybe it has major limitations in adition to the mentioned Windows linking issues? | 09:26 |
| pepijndevos | Of course eventually a nice C target is desirable, but at this point it's more of a proof of concept, with all the timing info and advanced knowledge still missing, so it'd be not far off from the simple.py example, and be mostly rewritten eventually anyway. | 09:29 |
| daveshah | The two limitations are performance (running the Python every time at startup might take 10-20s compared to 10ms to a bba linked into the elf) | 09:37 |
| daveshah | and the lack of custom validity checking/packing/etc | 09:37 |
| daveshah | the latter needed for useful clock enable, set/reset, advanced IO, etc | 09:38 |
| mwk | a lot of packing could be done as yosys passes though | 09:46 |
| daveshah | Yeah, this is true | 09:47 |
| pepijndevos | https://github.com/YosysHQ/nextpnr/blob/master/docs/generic.md also mentions a packer could be implemented in Python | 09:47 |
| tpb | Title: nextpnr/generic.md at master · YosysHQ/nextpnr · GitHub (at github.com) | 09:47 |
| daveshah | Yeah, it's mostly performance that's the issue | 09:48 |
| daveshah | The main part of packing that's a bit annoying to do in Yosys is clocking/IO stuff that requires some understanding of the physical layout | 09:50 |
| daveshah | stuff like what banks IO are in changing the IOLOGIC primitive used; merging/constraining DQS groups; etcc | 09:50 |
| pepijndevos | Yea, once I get to those kind of things it'll *definitely* be a C thing. | 09:51 |
| pepijndevos | But for now all I have is basically LUT, DFF([SR]E?), and basic, basic, IOB. So compared to the simple.py I only need to add more wires, and figure out the stuff about packing and constraint to some extend. | 09:53 |
| pepijndevos | But for now, even if set/reset/enable is not supported, fine with me. | 09:53 |
| pepijndevos | I guess the main thing is that in Gowin, a tiles has 4 slices of two DFF with a shared clock and set/reset, so I need to find out how to add that. | 09:54 |
| pepijndevos | But honestly, if the pnr for now assumes the whole tile shares clock and reset, that's probably good enough fow now. | 09:54 |
| daveshah | The generic arch comes with a toy packer that just combines FFs and LUTs into a LUTFF primitive, assuming a shared clock and no set/reset | 09:55 |
| daveshah | Just creating 8 of those per tile for the generic arch would be a very good start | 09:55 |
| daveshah | then you don't really have to do any packing or legality checking of your own at all | 09:56 |
| daveshah | There is also another script that is an example of a fasm backend for generic, if you wanted to use that as your bitstream IR | 09:58 |
| pepijndevos | ... within which scope does it assume a shared clock? | 09:59 |
| daveshah | It allows one clock per tile | 10:00 |
| daveshah | Given this is really intended for a proof of concept, it's most likely you'll only have one clock per design anyway.... | 10:00 |
| pepijndevos | Right | 10:00 |
| pepijndevos | I'm thinking if I can do this in a way that the bitstream packer doesn't depend on names in the generic target. | 10:07 |
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| blackbit | hi all. i read about this GW1N-1 FPGA recently. is there any leverage to support it in yosys and make something comparible to icestorm? | 13:22 |
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| pepijndevos | blackbit, I'm working on it :) | 13:35 |
| blackbit | nice | 13:35 |
| blackbit | you already have such a board? | 13:36 |
| pepijndevos | I have a Tang Nano with an GW1N-1 | 13:36 |
| blackbit | i am ordering two of them right now, though the seeed website is unbelievably slow right now | 13:37 |
| pepijndevos | blackbit, current status of Gowin support is that the Yosys side is fairly decent. Nextpnr not so much. I'm working towards some PoC flow now that can just barely route LUTs and DFF without any special options or hard IP blocks (bram, pll, etc) | 13:44 |
| pepijndevos | I tweet progress updates some times. | 13:45 |
| pepijndevos | Meanwhile working on making a wireless display with one of these ASK breakout boards that talks with Virtualwire/Radiohead: https://github.com/pepijndevos/vhdlwire/ | 13:46 |
| tpb | Title: GitHub - pepijndevos/vhdlwire: A VHDL implementation of VirtualWire/RadioHead (at github.com) | 13:46 |
| blackbit | nice | 13:48 |
| blackbit | twitter handle? | 13:48 |
| pepijndevos | pepijndevos | 13:48 |
| pepijndevos | Yosys PR with some extra stuff: https://github.com/YosysHQ/yosys/pull/1449 | 13:50 |
| tpb | Title: Improvements for gowin support by pepijndevos · Pull Request #1449 · YosysHQ/yosys · GitHub (at github.com) | 13:50 |
| blackbit | thanks | 13:51 |
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| pepijndevos | How does one use bugpoint? With the default options it seems to delete the toplevel module and then say all simplifications are exhausted. | 15:49 |
| pepijndevos | What I'm currently doing is read_velilog on a design, and then bugpoint -script with something that does an equivalence check on synthesis | 15:50 |
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| ZirconiumX | pepijndevos: are you triggering something | 17:48 |
| ZirconiumX | If you are, then you should use `-grep` | 17:50 |
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| ZirconiumX | So, I'm trying to implement the yosys test/arch/common tests, and proc_dff bails out with "ERROR: Multiple edge sensitive events found for this signal!" | 22:25 |
| ZirconiumX | I'm probably doing something wrong, but what? | 22:25 |
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