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| ZipCPU | pepijndevos[m]: Synchronization with a (slow) digital stream should be easy. 1) Matched filter (boxcar should work nicely), 2) multiply data with itself delayed by a half a bit (just xor the MSBs), 3) run a PLL on the result | 13:56 |
|---|---|---|
| ZipCPU | See: https://zipcpu.com/dsp/2017/12/14/logic-pll.html | 13:56 |
| tpb | Title: Building a Simple Logic PLL (at zipcpu.com) | 13:56 |
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| pepijndevos | ZipCPU, Interesting, I'll read it later. This is what I have now: https://github.com/pepijndevos/vhdlwire/blob/master/src/receiver.vhd#L107 | 22:02 |
| tpb | Title: vhdlwire/receiver.vhd at master · pepijndevos/vhdlwire · GitHub (at github.com) | 22:02 |
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| ZipCPU | Do you understand how that algorithm works? | 22:03 |
| pepijndevos | ZipCPU, uuhhh, kinda | 22:04 |
| ZipCPU | <smiles boardly> | 22:04 |
| ZipCPU | *broadly | 22:05 |
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| pepijndevos | ?? | 22:05 |
| pepijndevos | It's way past bedtime over here, but will happily talk RF stuff tomorrow | 22:06 |
| ZipCPU | It might take more time than IRC can give it | 22:06 |
| ZipCPU | Thanks for posting it, though. It really helps me to understand what you are working with | 22:06 |
| pepijndevos | (at the top is also links the C source, but I think I shared that already) | 22:07 |
| ZipCPU | I think I can get a quick grasp for how it's working just from that alone | 22:07 |
| ZipCPU | (I don't remember seeing it before ...) | 22:07 |
| ZipCPU | Ouch ... that replacement must've been quite painful | 22:08 |
| pepijndevos | It's basically a *very* crude PLL that counts a bit faster or slower if a transition happens before or after it expects it. | 22:08 |
| pepijndevos | What I don't get... is how it rejects spurious transitions.... but maybe it just doesnt | 22:10 |
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