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| emeb_mac | it's been a few months since I last tried to build yosys. just pulled from git and tried to build and got this clang crash: https://pastebin.com/0bfU2aEi | 04:47 |
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| emeb_mac | Note - this is on an RPi4 w/ latest raspbian | 04:47 |
| emeb_mac | yosys previously built fine on this HW, but with earlier raspbian. | 04:48 |
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| turq | I'm new to fpga, and I have a question about how to go about debugging a problem | 16:12 |
| turq | Here are the details: https://gist.github.com/turqq/301b02a1f16252479e7ba0b2a4bbdae2 | 16:12 |
| tpb | Title: 1q.md ยท GitHub (at gist.github.com) | 16:12 |
| turq | if anyone is able to give some feedback, I would very much appreciate it since I'm sort of stuck :) | 16:12 |
| daveshah | First of all, I would create a design that just uses an `assign` to connect rx to tx | 16:13 |
| daveshah | That will loop characters around and test that the serial port is working | 16:13 |
| daveshah | I would also check that baud rate etc is set correctly | 16:14 |
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| turq | thank you daveshah. I have checked the baud rate, I'll try the assign statement | 17:10 |
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