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| Noname_Matt | test. | 00:26 |
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| mwk | toast. | 00:29 |
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| matthuszagh | hello. i'm having some trouble getting yosys to find verilog include files via a tcl script. I must be doing something obviously wrong but I can't pinpoint it. If I write the read_verilog line as 'read_verilog -sv -I/path... top.v' it works fine, but if I place the same string in an environment variable and read it out with $::env(INCLUDES) yosys emits an error saying it can't open the include file. I've checked that tcl gets the | 02:27 |
| matthuszagh | variable with puts $::env(INCLUDES) and it matches what I expect | 02:27 |
| matthuszagh | happy to post the actual scripts and output if that helps | 02:29 |
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| Noname_Matt | matthuszagh How are you calling yosys with the includes? | 03:03 |
| Noname_Matt | I ran into a (sort of) glitch in TCL like this | 03:04 |
| Noname_Matt | if you read it in like | 03:04 |
| Noname_Matt | set my_var "item1 item2 item3" | 03:04 |
| Noname_Matt | then call it like | 03:04 |
| Noname_Matt | exec "yosys" $my_var | 03:05 |
| Noname_Matt | you may get this problem as the three items are passed as one item with spaces in it | 03:05 |
| Noname_Matt | this is not a system() call. it's directly calling the exec() system call | 03:05 |
| Noname_Matt | the workaround is to do | 03:05 |
| Noname_Matt | eval exec "yosys" $my_var | 03:06 |
| Noname_Matt | which adds an extra level of evaluation which breaks apart the list | 03:06 |
| Noname_Matt | be careful about attacker controlled variable contents though, as this is adding an extra iteration of evaluation after all | 03:07 |
| matthuszagh | Noname_Matt: the way I call it is a bit different. I have a makefile with an export command at the top, then variable definitions then just yosys path/to/script.tcl | 03:08 |
| matthuszagh | i'm trying to come up with a minimal example that introduces, but so far it's working there... | 03:08 |
| matthuszagh | s/introduces/reproduces/ | 03:08 |
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| Noname_Matt | ah, ok. I'm not familiar with yosys' internal TCL interfaces and interpreter | 03:09 |
| matthuszagh | thanks anyway! | 03:09 |
| Noname_Matt | though I have plenty of experience with synopsys' :P | 03:10 |
| Noname_Matt | need to learn more about yosys and the icestorm flow | 03:10 |
| Noname_Matt | I've only done some small proof of concept stuff so far | 03:10 |
| matthuszagh | ah was just about to ask if there's a way around the tcl usage (i.e. get a enviro variable from a yosys script) but i guess then you probably wouldn't know | 03:11 |
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| Noname_Matt | can you do something like | 03:40 |
| Noname_Matt | yosys --includes $includes | 03:41 |
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| Guest4992 | argh. battery picked that exact instant to die | 03:46 |
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| matthuszagh | Noname_Matt: that doesn't appear to work either | 03:46 |
| Noname_Matt | It probably wouldn't. I was making up the command line option. | 03:46 |
| Noname_Matt | My point was rather can you have the calling makefile derefeence the variable? | 03:47 |
| Noname_Matt | dereference* | 03:47 |
| matthuszagh | oh yeak ok i see. unfortunately i don't think yosys has an include flag like that | 03:48 |
| matthuszagh | just via yosys -p | 03:48 |
| matthuszagh | I've filed a bug report, seems like it may be one | 03:50 |
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| Noname_Matt | anyone remember offhand what the maximum clock frequency of the RISCV core that can be implemented on the HX8K is? | 14:02 |
| daveshah | About 60MHz | 14:04 |
| daveshah | for both picorv32 and vexriscv | 14:04 |
| daveshah | 70MHz might be doable with optimum config and good luck | 14:04 |
| rvense | how many clocks per instruction? | 14:06 |
| daveshah | picorv32 is around 3, vex is probably less than that | 14:07 |
| tnt | vex is also lower fmax though. | 14:16 |
| tnt | (at least on the up5k that's been my experience, for a minimal config) | 14:16 |
| Noname_Matt | Isn't the HX series a bit faster? | 14:18 |
| daveshah | Yes, but relative fmax would probably be simila | 14:18 |
| Noname_Matt | why is that? | 14:19 |
| daveshah | Because the up5k is roughly proportionally slower than the hx8k | 14:19 |
| Noname_Matt | I don't follow. If the HX series is faster (Wikipedia quotes 7.30 ns versus 9.00–9.36 ns which is around 25% improvement), wouldn't the maximum frequency for the core likewise be faster on one of the HX devices? | 14:22 |
| daveshah | Yes | 14:22 |
| daveshah | But it probably doesn't change picorv32 being higher fmax than vex | 14:22 |
| Noname_Matt | ah | 14:23 |
| daveshah | (idk what that wiki number is but the difference is more like 2-3x) | 14:23 |
| Noname_Matt | so would 60MHz be representative of the faster chips? | 14:23 |
| daveshah | Yes, that was in the context of an hx8k | 14:24 |
| Noname_Matt | so maybe 20-30MHz on other devices? | 14:24 |
| daveshah | Yeah | 14:25 |
| daveshah | tnt probably has more experience here | 14:25 |
| tnt | On the UP5k meeting 24 MHz with picorv is not too hard. I also have a design where it's at 30.72 MHz, but that one requires quite a bit of trying seeds to pass timing. | 14:33 |
| tnt | It can vary wildly depending on what you put on the memory bus obviously ... | 14:34 |
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