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| ZipCPU | rvense: Have you tried the yosys "show" command? | 12:09 |
|---|---|---|
| ZipCPU | It works great on small (as in *really* small) designs, but can be useful to see what's going on within them. | 12:10 |
| rvense | ZipCPU: yeah, that's what i was looking at, but i'm a bit confused by some of the output | 12:15 |
| rvense | ovals with numbers in them are... constants? what about the roundrects? | 12:16 |
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| ZipCPU | rvense: Not sure about the round rects, but IIRC the ovals with constants are inputs or outputs of the selection | 12:50 |
| ZipCPU | There are also bit-selects. Despite seeing them often, I'm not quite certain what to make of them (yet) | 12:54 |
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| mwk | bit-selects happen whenever you have a connection that isn't full-bus to full-bus | 13:05 |
| rvense | http://www.clifford.at/yosys/files/yosys_appnote_011_design_investigation.pdf | 13:06 |
| mwk | ie. if you pick bits 3:2 of an 8-bit output to connect to your 2-bit input, you'll see something like 3:2-1:0 | 13:06 |
| rvense | find some explanations in there | 13:06 |
| ZipCPU | Oh, okay ... that's always confused me. So 3:2 are the bit-select in the units of the original vector, and 1:0 are the valid bits of the new/output vector | 13:08 |
| ZipCPU | That's always confused me | 13:08 |
| mwk | yes | 13:08 |
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