Thursday, 2019-10-17

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somlofpga related article on LWN.net, mentioning yosys/trellis/nextpnr: https://lwn.net/SubscriberLink/801928/25775f5d4b1ec6c400:42
tpbTitle: FPGAs and free software [LWN.net] (at lwn.net)00:42
whitequark>One problem with the LUT-based mechanism is that it is slower than using a "real" gate as the MUXes are driven by a clock, so each level of MUX (e.g. two levels for the two-input XNOR) adds some delay.00:44
whitequarkum, what?00:44
sorearaddressed in the comments at least00:51
gruetzkopfehm, someone is confusing FFs with muxes?00:51
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chipbbwidawsk: ^^^03:23
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bwidawskugg03:42
bwidawskof all the times I present at XDC, lwn picks the one time I don't talk about graphics to make an article03:43
bwidawskhopefully at least it helped bring some eyes to the projects03:45
bwidawskeven if I didn't have all the facts right03:45
chipbI guess graphics aren't exotic enough to make the cut, huh?03:45
chipbI thought your intro was a reasonable approximation. the audience for the most part are circuit consumers, not designers.03:48
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chipber, by my presumption, I mean.03:49
bwidawskyeah, I think also for the fake example I had, it was accurate03:49
bwidawskor close enough03:49
bwidawskperhaps I should have spent more effort to explain real FPGAs don't work like the example03:54
whitequarka LUT is pretty much a 1-bit wide asynchronous SRAM, isn't it?03:59
bwidawskyeah, but the way I chained them up to make an n-LUT out of a 2-LUT03:59
bwidawskin my example03:59
whitequarkmhm04:00
whitequarki'm still not sure where the clock comes from04:04
chipbI took it more as a combinatorial logic delay tick moreso than a literal clock input to a FF.04:07
chipbI guess I'd agree that the wording might've been more precise, but given I believe it was effectively a room full of laymen... *shrug*04:18
whitequarkit's just a pity, given the rest of the article is quite good04:32
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