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| promach | I have used https://github.com/YosysHQ/nextpnr/blob/master/docs/constraints.md , why still "Warning: No clocks found in design" ? | 02:48 |
|---|---|---|
| tpb | Title: nextpnr/constraints.md at master · YosysHQ/nextpnr · GitHub (at github.com) | 02:48 |
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| janrinze | promach: do you have a clock? | 10:36 |
| promach | janrinze: I have clk in my verilog | 10:42 |
| janrinze | promach: is your verilog desing on github? | 10:50 |
| janrinze | promach: might be easier to look at the verilog code and assess what the issue is. | 10:51 |
| promach | janrinze: https://gist.github.com/promach/cf3ae626a85badad6cd822d3107c86b7 | 10:55 |
| tpb | Title: Spidergon Networks On Chip · GitHub (at gist.github.com) | 10:55 |
| janrinze | promach: datainput and dataoutput are missing in NoC module .. try adding like module NoC #(...) (clk,rest,data_input,data_output); | 11:00 |
| janrinze | promach: if those are not driven nor used as output then Yosys can optimize them out and the result will be an empty design. | 11:01 |
| promach | janrinze: No | 11:05 |
| promach | NoC.v is used to encapsule the spidergon NoC | 11:05 |
| promach | data_input and data_output need hardware pins if without NoC.v | 11:05 |
| promach | do you understand what I mean ? | 11:05 |
| janrinze | when you build with yosys, what is the 'top'? | 11:20 |
| promach | janrinze: see https://gist.github.com/promach/cf3ae626a85badad6cd822d3107c86b7#file-spidergon-ys | 11:21 |
| tpb | Title: Spidergon Networks On Chip · GitHub (at gist.github.com) | 11:21 |
| promach | line 9 | 11:22 |
| janrinze | top=NoC thus no inputs for data_input and data_output | 11:22 |
| janrinze | so if you add then to the module definition of NoC the accompanying pins will be retrieved from the constraints file. | 11:24 |
| janrinze | the top module in your design only has clk and reset. | 11:25 |
| promach | janrinze: there is no need for hardware IO pins for data_input and data_output | 11:25 |
| promach | do you understand what I mean ? | 11:25 |
| janrinze | then yosys will consider those irrelevant to the design and optimise out. | 11:26 |
| janrinze | promach: how about you just try to add them as pins and then look at the result. | 11:28 |
| janrinze | a design that is not connected can be optimized away. and thus no clock necessary either | 11:29 |
| promach | janrinze: not enough hardware IO pins | 11:29 |
| promach | on FPGA | 11:29 |
| promach | janrinze: I just found some logic loop issues, let me solve those those first | 11:32 |
| janrinze | promach: does not matter, you don't need to have real hardware to run yosys. the pin assignment only happens in nextpnr anyway. | 11:33 |
| promach | yes, but data_input and data_output takes out too many IO pins | 11:34 |
| promach | do you understand ? | 11:34 |
| promach | not enough pins to assign, even inside nextpnr | 11:34 |
| janrinze | hrmm.. how about creating a simple mux that is connected to io pins. then at least yosys can see that all input and output pins are used. | 11:35 |
| promach | huh ? | 11:37 |
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| janrinze | promach: you can try using "setattr -set keep 1" in the spidergon.ys file on line 8. | 12:07 |
| janrinze | it might help keeping the design from being optimized away. and you cna then run nextpnr-ice40 to see if the design fits and what fmax is. | 12:08 |
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| promach | janrinze: thanks, but I need to solve some logic loop issues first | 14:22 |
| promach | that is more important now | 14:22 |
| * promach just solved those loop issues | 16:46 | |
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