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| janrinze | daveshah: Any chance we will see updated tools that properly write to the flash of ECP5 eval board? | 11:45 |
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| ZipCPU | janrinze: What ECP5 eval board are you using? | 14:39 |
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| ZipCPU | I just ask because ... I've been writing to the external (QSPI) flash chips for some time on Xilinx/Intel/iCE40/ECP5 boards without too much hassle | 14:52 |
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| janrinze | ZipCPU: the one from lattice. http://www.latticesemi.com/ecp5-evaluation | 15:33 |
| tpb | Title: ECP5 Evaluation Board - Lattice Semiconductor (at www.latticesemi.com) | 15:33 |
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| ZipCPU | Bummer. I was hoping it would be the one I was working with: http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/ECP5VersaDevelopmentKit.aspx | 15:36 |
| tpb | Title: ECP5 Versa Development Kit - Lattice Semiconductor (at www.latticesemi.com) | 15:36 |
| ZipCPU | The problem with a "generic" flash writer is that ... there are so many different incompatible flash devices out there | 15:36 |
| ZipCPU | My own "generic" solution depends upon software to detect the flash, and then add in special commands for certain flash chips. It's by no means complete. | 15:37 |
| ZipCPU | http://zipcpu.com/blog/2019/03/27/qflexpress.html | 15:37 |
| tpb | Title: Building a universal QSPI flash controller (at zipcpu.com) | 15:37 |
| ZipCPU | I also just updated the ECP5 demo: https://github.com/ZipCPU/zipversa/tree/dev | 15:39 |
| tpb | Title: GitHub - ZipCPU/zipversa at dev (at github.com) | 15:39 |
| janrinze | The versa board is nice. I prefer stand-alone boards myself. | 15:45 |
| ZipCPU | I'm using it as a stand-alone ;) | 15:45 |
| ZipCPU | I have yet to fire up either the SDRAM or the PCIe interface | 15:45 |
| ZipCPU | That said, it's not the board that you have, so my work might (or might not) help you :/ | 15:46 |
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| janrinze | does your build flash the design or just upload it to the ecp5? | 15:50 |
| janrinze | I see in the .cfg that openocd will program the ecp5 | 15:50 |
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| ZipCPU | The openOCD is used to load the design into the FPGA via JTAG. The zipload.cpp program (based upon flashdrvr.cpp) is used to actually write to the flash once the design is loaded. | 15:53 |
| ZipCPU | You can find both zipload.cpp and flashdrvr.cpp in the sw/host directory, since they'll run from an external (PC) host | 15:54 |
| janrinze | would this work over USB? the versa has PCI-bus, right? | 15:58 |
| ZipCPU | I use it over a USB serial port, yes | 15:58 |
| janrinze | Okay. interesting. I can try build it and see how that goes, | 15:59 |
| ZipCPU | This particular design also has some amount of serial port compression going over the command channel | 15:59 |
| janrinze | i remember that compression was particularly difficult with programming the ecp5 | 15:59 |
| ZipCPU | I didn't say that I was compressing the ECP5 image, just the serial port command channel | 16:00 |
| janrinze | okay. Does the zipcpu write the flash? | 16:00 |
| ZipCPU | No | 16:01 |
| janrinze | ah. good. | 16:01 |
| ZipCPU | The dev branch doesn't even have the ZipCPU enabled in it anymore--the customer wanted a picoRV | 16:01 |
| ZipCPU | That said, the PicoRV isn't involved in writing the flash either. | 16:01 |
| ZipCPU | You can see a picture of the serial port command channel processing in Fig 1 of this post: http://zipcpu.com/blog/2017/06/05/wb-bridge-overview.html | 16:03 |
| tpb | Title: An Overview of a Wishbone-UART Bridge (at zipcpu.com) | 16:03 |
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| janrinze | so it requires the wishbone-uart bridge. | 16:14 |
| ZipCPU | You'd need something to communicate data from the PC/host to the FPGA | 16:15 |
| janrinze | in order to make that work, first the design with a wishbone-uart bridge needs to be uploaded to the FPGA, correct? | 16:15 |
| ZipCPU | Yes | 16:16 |
| janrinze | okay, a two stage uploader would work, i guess. | 16:16 |
| ZipCPU | I think that's the way most of the commercial loaders work | 16:16 |
| janrinze | currently I use the python script that creates a script for openocd. | 16:16 |
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