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| mkru | Is yosys somehow connected with Verific company or it is just coincidence, that in script we can use verific keyword? | 08:37 |
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| tnt | mkru: There is a commercial version of yosys that integrates with verific. | 08:41 |
| emily | hm, is the version of yosys itself commercial? I thought the Verific code was all open in the repositories | 08:44 |
| emily | as in, the Verific-integrating code | 08:44 |
| daveshah | I believe there are some patches to Verific that are not open source | 08:44 |
| daveshah | And also a license manager which is not open source | 08:45 |
| daveshah | Most of the glue is in the open source Yosys though | 08:45 |
| mkru | tnt: Do you know what are the prons of commercial version? | 08:48 |
| mkru | pros* | 08:49 |
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| tnt | mkru: I never used it. But among them are System Verilog support, the dot notation for internal signals and VHDL support. | 08:55 |
| tnt | (I know those in particular because they're stuff I'd like to use but are not avail :p) | 08:55 |
| mkru | Ok, I am a bit confused. I thought that verific is used under the read command? | 09:05 |
| daveshah | The read command uses Verific if available or the FOSS frontend otherwise | 09:07 |
| mkru | So how much of this https://symbiyosys.readthedocs.io/en/latest/verific.html is available without buying any license? | 09:30 |
| tpb | Title: SystemVerilog, VHDL, SVA SymbiYosys 0.1 documentation (at symbiyosys.readthedocs.io) | 09:30 |
| emily | I think you can do some SystemVerilog stuff with just the free software toolchain, though I'm not 100% certain on that. | 09:42 |
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| mkru | The more I read, the more I get a feeling that SymbiYosys is just a marketing product, not an open source tool. To use it in a big, complex projects you still need to buy licenses. | 09:52 |
| emily | I think there's the intention to improve SystemVerilog support in the all-Free toolchain, it just needs someone to actually put in the work | 10:22 |
| emily | rebuilding entire commercial toolchains that have had decades to develop and mature from the ground up isn't easy | 10:23 |
| mkru | emily: Does it require improvements in frontend, backend or both? Do you know? | 10:32 |
| emily | the frontend would definitely need work; I've heard talk about adding more common SV features being blocked on some parser troubles or something? But I'm really not the person to ask, I'm still an amateur and haven't used SV at all yet ^^; | 10:33 |
| emily | there's also ##openfpga btw, where azonenberg is talking about adding SystemVerilog features to yosys right now in fact | 10:33 |
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| ZipCPU | mkru: @(posedge clk) and @(negedge clk) are both supported by FOSS yosys .... ;) | 10:49 |
| tnt | lol | 10:51 |
| tnt | negedge should definitely be a premium feature, who needs that ... | 10:51 |
| ZipCPU | mkru: I've been through the parser a couple times. It works, but there's discussion that it could use a rewrite. To my knowledge, no one is working on that | 10:51 |
| ZipCPU | I'm not sure if the native parser would be up to SystemVerilog | 10:52 |
| ZipCPU | That said, I've looked over many of the missing features and there's been more than once when I seriously thought of adding them in | 10:52 |
| ZipCPU | For example, $onehot and $onehot0 would be valuable to me, and not all that hard to add in | 10:52 |
| mkru | I would like to contribute but C++ is a big issue for me. | 10:52 |
| mkru | I wish I could use Rust. | 10:52 |
| ZipCPU | I'd also like to be able to do simple single-clock SVA assertions: assert property (@(posedge i_clk) disable iff (A) B |=> C); Those shouldn't be so hard, but been busy enough with other projects that I haven't dug into that | 10:54 |
| ZipCPU | IIRC, Clifford committed to implementing the dot notation, and if you look hard enough you'll find some support for it | 10:55 |
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| ZipCPU | One of the issues was associated with finding the width and the type of the sub-module value | 10:55 |
| ZipCPU | The bottom line, however, is that all this work costs money and ... unless someone ponies up to pay for it, the paying customers will get all the support | 10:56 |
| ZipCPU | I know there was one customer who was going to fund a full SystemVerilog back end, but then dropped out before the agreement could be finalized | 10:57 |
| ZipCPU | I also know there are several folks working on integrating various VHDL back ends ... those might become useful soon enough | 10:57 |
| ZipCPU | Sorry, VHDL front ends, not back ends | 10:58 |
| ZipCPU | The biggest problem I've heard from the VHDL front ends is that simple/basic support is easy to do, but no one has invested the time to get full feature support | 10:58 |
| mkru | Actually, what is front end responsible for and what is back end responsible for? Verilog has both. | 11:02 |
| daveshah | The front end reads and elaborates Verilog into Yosys' internal representation (RTLIL), the backend writes that out as Verilog | 11:03 |
| daveshah | Only the front end would need significant work for SystemVerilog (for the most part SV features would be lost during elaboration anyway, so there would be no changes to what the backend needs to write) | 11:04 |
| hackerfoo | There is effort on open source SystemVerilog support, but it will take time. | 11:07 |
| mkru | Any project that look promising? | 11:08 |
| hackerfoo | https://github.com/zachjs/sv2v | 11:09 |
| tpb | Title: GitHub - zachjs/sv2v: SystemVerilog to Verilog conversion (at github.com) | 11:09 |
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| hackerfoo | If anyone wants to contribute, let us know on #symbiflow. We could use some help :) | 11:14 |
| mkru | Are you the owner? | 11:16 |
| hackerfoo | mithro is the lead. I've been working on the project since April. | 11:18 |
| hackerfoo | (SumbiFlow, not sv2v) | 11:19 |
| hackerfoo | *SymbiFlow | 11:20 |
| mkru | What do you focus your work right now? | 11:23 |
| mkru | on* | 11:23 |
| hackerfoo | I'm working on Xilinx 7 series support. | 11:29 |
| hackerfoo | We're working towards Linux on a SoC on an Artix 7. | 11:34 |
| mkru | Sounds nice. Do you have any topics, that sounds like potential PhD thesis? | 11:36 |
| hackerfoo | mkru: I'm sure I could help you find one. We're using Verilog to Routing (https://verilogtorouting.org/), which is used in academic research. | 11:41 |
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| mithro | mkru: plenty of potential PhD thesis projects | 16:03 |
| mithro | mkru: if your interested, happy to work with you to find something which matches your and your unis interests | 16:04 |
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