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| promach | What does "loop warning" means for "ltp -noff" ? Can I just ignore the loop warning ? | 05:33 |
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| janrinze | a bit curious here.. the ecp5 evaluation board runs the design well after uploading with the openocd tools through make. | 18:08 |
| janrinze | But after powercycle the design has reverted to the default design of lattice. | 18:08 |
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| ZirconiumX | janrinze: FPGAs are volatile devices | 18:13 |
| ZirconiumX | It's possible it didn't get written to the flash or whatever | 18:14 |
| janrinze | that's the point here. normallly the tools ensure a wrtite to flash | 18:14 |
| janrinze | oops .. 'write' | 18:17 |
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| daveshah | There are a few scripts lurking for programming ECP5 SPI flash rather than SRAM over JTAG | 18:31 |
| daveshah | I don't have links to any off hand though | 18:31 |
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| tnt | daveshah: is that using bscan or uploading a bitstream to the fpga that allows it to bridge jtag to spi flash ? | 20:15 |
| daveshah | There is some kind of built in SPI over JTAG "tunnelling" | 20:15 |
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| janrinze | daveshah: I've been looking around but all the makefiles look the same with the same svf scripts | 21:17 |
| cr1901_modern | daveshah: While it's on my mind, when andresnavarro RE'd the compression code, were you ever able to test it on ECP5 family? | 21:18 |
| daveshah | janrinze: I don't think any of the prjtrellis examples use it. I think it was done by Greg: https://gist.github.com/gregdavill/4f9f536757966171ef974f98348bbacb | 21:24 |
| tpb | Title: background_spi_test.py ยท GitHub (at gist.github.com) | 21:24 |
| daveshah | cr1901_modern: no, I don't think I ever did | 21:25 |
| cr1901_modern | Just wondering is all :P | 21:25 |
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| janrinze | daveshah: Greg seems to have several nice ecp5 projects on github. Mostly kicad and strangely the python script i could not find in github, only on the gist | 21:56 |
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