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| GenTooMan | I found a yosys bug report in June, no wonder my verilog stuff doesn't work. Sorry had to be said. It optimizes out my psuedo write code, then the bug occurs as it expects ONLY a read after write not just a read, or read before write. | 16:06 |
|---|---|---|
| GenTooMan | next to implement write only memory... | 16:07 |
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| emeb | I've got a bogus datasheet for "Nominal Semidestructor Write-Only Memory" | 16:26 |
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| pepijndevos[m] | Which part of yosys detects bram? Is that done by the parser or by some extraction pass? I think the latter, right? | 20:54 |
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| daveshah | pepijndevos[m]: The parser creates `$memrd`, `$memwr` and `$meminit` | 21:00 |
| daveshah | `memory_dff` folds `$dff`s into these | 21:00 |
| daveshah | `memory_collect` converts these into combined `$mem` multiport memories | 21:01 |
| daveshah | `memory_bram` maps `$mem` to bram according to arch-specific rules (usually followed by `techmap` to map to arch primitives exactly) | 21:01 |
| pepijndevos[m] | Ah OK, but if ghdl just creates a bunch of dff, there is no pass that translates those to memory cells | 21:08 |
| pepijndevos[m] | Haven't tried yet, but I suspect ghdl does not yet have any special logic to infer memory. | 21:08 |
| pepijndevos[m] | Of course an alternative would be to blackbox the vendor primitive. | 21:09 |
| pepijndevos[m] | Or by fold into you mean memory_dff will actually create new cells, rather than fold dff into adjacent memory cells? | 21:12 |
| pepijndevos[m] | I'll look at the docs and ghdl tomorrow | 21:12 |
| daveshah | No, Yosys can't create memories out of DFFs and muxes | 21:12 |
| daveshah | `memory_dff` is only for folding dffs to create clocked read/write ports | 21:12 |
| daveshah | You will need to modify ghdl to create read and write port cells | 21:13 |
| pepijndevos[m] | Alright | 21:13 |
| shapr | howdy pepijndevos[m] ! | 21:37 |
| shapr | I've enjoyed your blog posts! | 21:38 |
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| somlo | can yosys take advantage of multithreading (e.g., on a multi core machine)? | 23:26 |
| ZirconiumX | somlo: no | 23:33 |
| somlo | is it the nature of the workload that lacks parallelism, or just a thing nobody had a chance to get around implementing -- yet? | 23:34 |
| ZirconiumX | somlo: Partly A, partly that the algorithms Yosys uses are not well-suited to parallelism | 23:35 |
| shapr | I'd expect nextpnr and arachne would be GREAT with a bunch of cores | 23:36 |
| ZirconiumX | arachne is all but dead | 23:36 |
| * shapr updates his cache | 23:36 | |
| somlo | I dug around the git log of nextpnr and saw a bunch of commits mentioning multithreading, so I'm hopeful :) | 23:36 |
| somlo | for now I'm watching yosys use one of my 8 rv64gc qemu VCPUs (building ecp5 bitstream for litex+rocket-rv64gc "natively") | 23:38 |
| somlo | and started wondering if there's any way to make it faster :) | 23:38 |
| ZirconiumX | Yosys does lots of little things to optimise it | 23:39 |
| ZirconiumX | So there's very little to gain by parallelising one specific pass | 23:39 |
| shapr | is nextpnr simulated annealing? | 23:40 |
| ZirconiumX | I think that's one of the algorithms it can use | 23:40 |
| shapr | ok now you got me interested | 23:40 |
| ZirconiumX | nextpnr was born because arachne was too hard-coded for iCE40 | 23:41 |
| ZirconiumX | It couldn't handle ECP5 without major rework | 23:41 |
| ZirconiumX | Thus nextpnr was built as a framework | 23:41 |
| shapr | spiffy | 23:41 |
| somlo | I noticed (from a user perspective) how yosys does multiple "passes" or "stages" - I'm assuming those can't be pipelined either, one's got to finish before its complete output can be used by the next stage... | 23:44 |
| ZirconiumX | somlo: Correct | 23:50 |
| somlo | and if I had to guess, most of the stages are heavy on graph manipulation, so maybe even if one could throw parallelism at it, the overhead might not be worth the trouble | 23:56 |
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