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| pepijndevos | How does the extract pass work with parameters? | 12:51 |
|---|---|---|
| pepijndevos | -ignore_parameters Do not use parameters when matching cells. | 12:53 |
| pepijndevos | So what does it do to "use parameters"? | 12:53 |
| pepijndevos | It seems extract is also extremely picky about using for example 1 or 8'b1 | 13:01 |
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| pepijndevos | Does a techmap "inherit" the parameters of the thing it replaces? | 15:16 |
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| pepijndevos | Are there any magic rules for when a techmap matches or not? Mine does not, for some reason. | 15:57 |
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| pepijndevos | ERROR: (ASSERT MODE) No matching template cell for type \$counter16 found. | 16:06 |
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| ZirconiumX | [16:07:31] pepijndevos: Does a techmap "inherit" the parameters of the thing it replaces? | 16:15 |
| ZirconiumX | If you use a _TECHMAP_REPLACE_ I think so | 16:16 |
| ZirconiumX | [16:48:29] pepijndevos: Are there any magic rules for when a techmap matches or not? Mine does not, for some reason. | 16:16 |
| ZirconiumX | Either the module is named the same as the cell you're trying to replace, or you have (* techmap_replace = "target_cell" *) above it, and _TECHMAP_FAIL_ is zero | 16:17 |
| ZirconiumX | That's when it matches | 16:17 |
| pepijndevos | ZirconiumX, it's the dollar signs... If I'm trying to act cool and put dollar signs in my counter like a real techmap it fails | 16:22 |
| pepijndevos | If I just extract and techmap without the dollars it breaks. I think I'm not escaping stuff enough/too much | 16:23 |
| ZirconiumX | The documentation says techmap -assert errors out if a cell name doesn't end with an underscore | 16:24 |
| ZirconiumX | If you called your cell $counter16, that'll error because it does not end with an underscore | 16:24 |
| pepijndevos | https://github.com/YosysHQ/yosys/blob/master/passes/techmap/techmap.cc#L413 i think it means it'll ignore anything with an underscore if I read the code correctly | 16:25 |
| tpb | Title: yosys/techmap.cc at master · YosysHQ/yosys · GitHub (at github.com) | 16:25 |
| ZirconiumX | Correct | 16:25 |
| ZirconiumX | Conversely since your cell does not end in an underscore, it's an error | 16:25 |
| pepijndevos | Yea, but if I just put an underscore it'll not error and still not replace, I think it's purely that it never asserts on underscored things. | 16:27 |
| pepijndevos | So if I call my extracted cell counter16 and the techmap on counter16 all is good, but if I call my extraction $counter16 or \$counter16 or whatever, nothing works. | 16:28 |
| pepijndevos | Or even $_COUNTER16_ or anything else that I've tried. | 16:29 |
| pepijndevos | So I'm not understanding anything about the naming convention and escaping. Like, I've seen \$thing and \\$thing and $thing in various places | 16:29 |
| pepijndevos | I guess I don't really care about the dollar thing, except counter8 seems so common it might come up in normal code, so I thought I'd stick with what seems to be a convention for dollar signs for cells. | 16:30 |
| pepijndevos | Should I just call it 74xx_counter and be done with it? | 16:31 |
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| pepijndevos | Cool, techmap kinda works, simulation super broken. | 16:52 |
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| pepijndevos | it's working! Kinda?? | 17:28 |
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| ZirconiumX | pepijndevos: so when are you shipping a PicoSoC to me? | 17:32 |
| ZirconiumX | :^) | 17:32 |
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| pepijndevos | ZirconiumX, hopefully near the end of the holiday :^) | 17:50 |
| ZirconiumX | I think the multiplier would be painful | 17:50 |
| pepijndevos | The pwmled is now 7 chips | 17:50 |
| ZirconiumX | Because of counter recognition? | 17:50 |
| pepijndevos | Yes | 17:51 |
| pepijndevos | But it's extremely picky, so you pretty much have to want to use it. | 17:51 |
| pepijndevos | Originally I wanted to use an up/down counter, but it seems 74161 is pretty much the only thing that's still on sale. | 17:51 |
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| ZirconiumX | I don't think you can meaningfully reduce that benchmark any further | 17:52 |
| pepijndevos | With an up/down counter you could make a sweeeet stack pointer, but at least maybe this is somewhat useful as an instruction pointer. | 17:52 |
| pepijndevos | There is a sexy sexy 8-bit up/down counter IC, but I don't think it's sold anywhere. | 17:53 |
| ZirconiumX | Which model? | 17:53 |
| pepijndevos | 74x867 | 17:54 |
| ZirconiumX | pepijndevos: have you seen the 74x4040? | 17:59 |
| pepijndevos | eh, yea... can't remember the details | 18:00 |
| pepijndevos | 12 bits is a bit... odd, no preset, no up/down. So it could be a lot more efficient in some cases, and less useful in others. | 18:02 |
| pepijndevos | Right now I have to specifically extract counter8, counter16 etc. and counter12 seems... not very common. | 18:03 |
| ZirconiumX | Mmm | 18:03 |
| pepijndevos | So for example, if I want to use it as an instruction counter, I need preset for jumps | 18:05 |
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| pepijndevos | Although I'm not even convinced what I'm doing now will work for that... | 18:06 |
| pepijndevos | Well, lemme push and you can have a look at it. | 18:06 |
| GenTooMan | the 74hc191 still is produced? | 18:08 |
| ZirconiumX | True, and Farnell sell it | 18:11 |
| ZirconiumX | GenTooMan: though we prefer DIP over SOIC for this | 18:11 |
| GenTooMan | ZirconiumX Nexperia and TI still make the DIP version as far as I know. | 18:12 |
| sorear | kinda surprised you’re not just using quad nands etc | 18:12 |
| ZirconiumX | TI are the one who sell DIPs for Farnell, and it's on back-order | 18:12 |
| ZirconiumX | sorear: We're crazy not stupid | 18:12 |
| GenTooMan | at least you are not making it with transistors. | 18:15 |
| pepijndevos | 74x191 is actually a nice one maybe? Not really in AC or DIP but... it counts down. | 18:19 |
| GenTooMan | the reason I bothered pointing it out. | 18:19 |
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| pepijndevos | change.org petition: TI makes the whole 74xx series | 18:30 |
| pepijndevos | sorear, part of me wants to do NOR and recreate the Apollo Guidance Computer | 18:31 |
| daveshah | Why need a change.org petition when you have MPWs? | 18:31 |
| pepijndevos | daveshah, what's MPW? | 18:32 |
| daveshah | Multi project wafer | 18:32 |
| daveshah | Relatively cheap way of making custom silicon | 18:32 |
| pepijndevos | Are you suggesting I make an ASIC instead (boring), or produce my own 74xx chips (omg)? | 18:33 |
| pepijndevos | Any idea what it costs to do that kind of stuff? | 18:33 |
| daveshah | Latter | 18:33 |
| daveshah | Probably a few thousand euros minimum | 18:34 |
| pepijndevos | Okay, scrap the change.org, on to kickstarter hehe | 18:34 |
| GenTooMan | then your biggest issue would become buffering and someone to package the chips. a single 8 inch wafer can get you quite a few parts I suspect. | 18:35 |
| daveshah | Europractice 700nm, probably fine for any 7400, 300€/mm2, 5mm2 min | 18:36 |
| daveshah | For 30 samples, excluding packaging | 18:36 |
| ZirconiumX | That's a bit pricey, but would be funny | 18:37 |
| ZirconiumX | On the other hand, why not just fabricate a PicoSoC directly? | 18:37 |
| pepijndevos | That's what these Raven people did, no? | 18:38 |
| pepijndevos | Or why not both? | 18:38 |
| daveshah | That's already been done | 18:38 |
| daveshah | Indeed | 18:38 |
| ZirconiumX | pepijndevos: I'm going to disappoint you greatly | 18:39 |
| ZirconiumX | "In my experience writing counter + 1 and counter + 1'b1 already causes a mismatch" | 18:39 |
| ZirconiumX | Because 1'b1 is 1-bit, and 1 is 32-bit | 18:39 |
| pepijndevos | I know, but yosys optimizes the useless bits away | 18:40 |
| ZirconiumX | Sure, but they're semantically different and the compiler obviously has to keep semantics | 18:40 |
| pepijndevos | I guess... | 18:41 |
| daveshah | opt and wreduce should deal with the difference though | 18:41 |
| pepijndevos | It just makes the counter extraction not very flexible. | 18:41 |
| ZirconiumX | I'm reasonably sure Yosys turns, say, 4'b1 (i.e. 4'b0001) to 4'bxxx1 | 18:41 |
| ZirconiumX | But don't quote me on that | 18:42 |
| daveshah | Unlikely | 18:42 |
| pepijndevos | daveshah, if I put my extract pass *after* wreduce it doesn't match. | 18:42 |
| daveshah | What does the netlist look like after wreduce (`dump` and `show` are helpful)? | 18:43 |
| daveshah | You might want to use a wreduce'd counter (e.g. saved as il) as the needle in this case | 18:43 |
| pepijndevos | That might be a good one... | 18:44 |
| daveshah | After wreduce and clean, this produces three identical adders (A_WIDTH 4, B_WIDTH 1, Y_WIDTH 4, B connected to 1'b1) | 18:46 |
| daveshah | https://www.irccloud.com/pastebin/sKl9bVGj/ | 18:46 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 18:46 |
| pepijndevos | does opt do clean or are these different things? | 18:49 |
| daveshah | opt does clean too (I didn't use opt for this test as it would actually merge all three adders) | 18:50 |
| pepijndevos | yay that works | 18:53 |
| pepijndevos | Now I wonder if it gets used in *any* of the other benchmarks... | 18:53 |
| pepijndevos | The answer is no | 18:54 |
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| matt` | hello! i'm having some trouble understanding a yosys error message: "found error in internal cell" where it's complaining about cell $_DFF_PP1. I'm experiencing this when running `synth_xilinx`; `read_verilog` works fine (although I do get a warning about tri-state logic from the same file triggering the error message). Is there a possibility this error means I'm using a tristate representation not supported by yosys? What does that | 21:42 |
| matt` | error mean generally? That yosys isn't able to map the RTL to the available Xilinx cells? | 21:42 |
| matt` | i'm running the current git master version btw | 21:43 |
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| daveshah | matt`: I don't think this would be related to a tristate issue | 21:47 |
| daveshah | A "found error in internal cell" is a Yosys bug | 21:47 |
| daveshah | If your design isn't confidential, creating a Yosys issue would be helpful | 21:48 |
| matt` | daveshah: i'll try to get this down to a minimal example and raise the issue. Thanks for the help! By the way, what does it mean that tri-state has limited support? is there somewhere in the documentation that says what is and isn't supported in that regard? | 21:49 |
| daveshah | If it helps pinpoint the issue, a `$_DFF_PP1_` is the Yosys internal type for a single-bit D flipflop with an asynchronous set and rising edge clock | 21:50 |
| daveshah | In practice I don't think it's so much that only a subset of tristate functionality is supported, as that tristate has a lot of different possibilities and not everything has been tested | 21:51 |
| daveshah | This is particularly the case for the Xilinx flow which isn't so well used for designs with this kind of stuff | 21:52 |
| matt` | gotcha. thanks again | 21:54 |
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