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pepijndevos_ | Warning: Yosys has only limited support for tri-state logic at the moment. (../benchmarks/MCPU.v:61) | 10:20 |
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pepijndevos_ | Trying to synthesize https://github.com/cpldcpu/MCPU/blob/master/verilog/MCPU_0.1a.v and failing | 10:20 |
tpb | Title: MCPU/MCPU_0.1a.v at master · cpldcpu/MCPU · GitHub (at github.com) | 10:20 |
tnt | pepijndevos_: yeah. "assign data = states!=3'b001 ? 8'bZZZZZZZZ : accumulator[7:0]; " needs some change. | 10:26 |
tnt | Also, is that supposed to be a top level ? I mean tristate really only makes sense for IOs. No modern fpga has internal tristates. | 10:27 |
corecode | yea too bad that there is no easy way to communicate an output enable other than explicit second line | 10:27 |
corecode | but i guess it makes it more explicit | 10:27 |
pepijndevos_ | tnt, not totaly sure tbh, just some core I snatched from the web. | 10:29 |
corecode | tnt: do you think it would make sense to automatically convert tristates to (hidden) enable signals and then connect to buffer OE? | 10:32 |
corecode | seems messy and too implicit | 10:32 |
corecode | very behavioral, not RTL | 10:32 |
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maikmerten | with latest yosys master LUT usage is back to normal (nextpnr can pack things together nicely again) | 12:16 |
maikmerten | so thanks a lot! :-) | 12:16 |
maikmerten | with relut being at work and nextpnr being able to pack things again, LUT-usage overall is now lower than ever | 12:24 |
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maikmerten | f_max is also back to normal, which means ~35 MHz (which I'm used to, caused by a carry chain) vs. ~45 MHz (with the original relut branch merged, with the carry chain no longer being the critial path). I wonder how the pre-fix yosys/nextpnr flow managed that. | 12:33 |
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pepijndevos_ | Huh, I'm confused. Looking at rtlil.h I swear I saw the actual implementations of add* functions, but I can't find them. I guess I'm being thick. | 15:03 |
pepijndevos_ | git grep addAdd does not seem to find any actual implementation. | 15:03 |
pepijndevos_ | oh, addAdff is there alright... but where are the others... | 15:05 |
pepijndevos_ | ah... DEF_METHOD | 15:06 |
pepijndevos_ | Is $mux always two-way? Because there is a $_MUX4_ but I've never seen $mux4, yet in rtlil.h it seems only two-way. | 15:11 |
daveshah | Larger muxes would end up either as $pmux or $shiftx depending on coding style | 15:12 |
daveshah | Or perhaps even a tree of $mux if coded using a tree of ?: | 15:13 |
pepijndevos_ | ah ok | 15:14 |
pepijndevos_ | I was looking at this code https://github.com/tgingold/ghdlsynth-beta/blob/db6d9f374de1eb1c074c2b9828bc6d99055b3624/ghdl/ghdl.cc#L340 | 15:14 |
tpb | Title: ghdlsynth-beta/ghdl.cc at db6d9f374de1eb1c074c2b9828bc6d99055b3624 · tgingold/ghdlsynth-beta · GitHub (at github.com) | 15:14 |
pepijndevos_ | For a mux4 it indeed creates a tree of muxes, and was curious if that's the correct way to do it. | 15:14 |
daveshah | It's as good as any | 15:15 |
pepijndevos_ | Cool | 15:15 |
daveshah | I'm not sure why ghdl has a mux4 cell in the first place... | 15:15 |
pepijndevos_ | I'm going to try to add module instatiations. We'll see if just adding it as a cell and connecting wires does the job. | 15:16 |
daveshah | Yes, modulo parameterisation | 15:16 |
pepijndevos_ | I think that's handled on the ghdl side, but not totally sure. Tristan mentioned he implemented modules in synthization but not on the yosys side, so I thought I'd try doing something useful. | 15:18 |
daveshah | For anything that isn't a blackbox leaf cell, you'll probably want to strip parameters from the instance and give each parameterised variant a unique name | 15:19 |
pepijndevos_ | right | 15:19 |
maikmerten | is there a list of nextpnr python console commands? | 15:28 |
daveshah | No, unfortunately not | 15:31 |
maikmerten | ah, okay :-) | 15:33 |
daveshah | For querying the Arch database you can follow https://github.com/YosysHQ/nextpnr/blob/master/docs/archapi.md | 15:33 |
tpb | Title: nextpnr/archapi.md at master · YosysHQ/nextpnr · GitHub (at github.com) | 15:33 |
maikmerten | just wondering if there is a way to highlight critical paths in the graphical overview | 15:34 |
maikmerten | but perhaps stuff like that is not what the python console is actually meant for | 15:34 |
maikmerten | (I imagine it's more for orchestrating processing steps) | 15:34 |
daveshah | No, unfortunately there's no Python or C++ api to get critical paths yet | 15:35 |
daveshah | The timing stuff isn't really integrated very well | 15:35 |
maikmerten | it's still plenty neat :-) | 15:36 |
maikmerten | help() at the time being is a halt-and-catch-fire alias | 15:38 |
maikmerten | I guess that's because it's doing interactive stuff with stdin and stdout presumably | 15:39 |
daveshah | Tab completion should work | 15:40 |
maikmerten | it does! | 15:40 |
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pepijndevos_ | What's a blackbox module supposed to look like in `dump`? Currently ghdl just makes a module \name end | 16:40 |
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daveshah | It also needs ports and a blackbox attribute set on it | 16:40 |
pepijndevos_ | I thought as much... some work to do then. | 16:42 |
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